Inventor
BYRN JONATHAN W
US20 patents
⚠️ This page may combine multiple inventors who share the name “BYRN JONATHAN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
9 patentsUS5533020AJul 2, 1996
ATM cell scheduler
IBM197 citations98
US5533021AJul 2, 1996
Apparatus and method for segmentation and time synchronization of the transmission of multimedia data
IBM537 citations98
US5537408AJul 16, 1996
apparatus and method for segmentation and time synchronization of the transmission of multimedia data
IBM364 citations97
US5502833AMar 26, 1996
System and method for management of a predictive split cache for supporting FIFO queues
IBM67 citations96
US5737638AApr 7, 1998
System for determining plurality of data transformations to be performed upon single set of data during single transfer by examining communication data structure
IBM41 citations91
US5555387ASep 10, 1996
Method and apparatus for implementing virtual memory having multiple selected page sizes
IBM30 citations90
US5260942ANov 9, 1993
Method and apparatus for batching the receipt of data packets
IBM38 citations89
US6601122B1Jul 29, 2003
Exceptions and interrupts with dynamic priority and vector routing
IBM12 citations70
US7149218B2Dec 12, 2006
Cache line cut through of limited life data in a data processing system
IBM3 citations59
LSI CORP
7 patentsUS7496867B2Feb 24, 2009
Cell library management for power optimization
LSI CORP122 citations97
US7703059B2Apr 20, 2010
Method and apparatus for automatic creation and placement of a floor-plan region
LSI CORP9 citations84
US7263678B2Aug 28, 2007
Method of identifying floorplan problems in an integrated circuit layout
LSI CORP3 citations63
US7818695B2Oct 19, 2010
Redistribution of current demand and reduction of power and DCAP
LSI CORP3 citations62
US7380229B2May 27, 2008
Automatic generation of correct minimal clocking constraints for a semiconductor product
LSI CORP5 citations54
US7966592B2Jun 21, 2011
Dual path static timing analysis
LSI CORP1 citations52
US7787325B2Aug 31, 2010
Row decode driver gradient design in a memory device
LSI CORP0 citations41