Inventor

KIM KYU-HYOUN

US192 patents

⚠️ This page may combine multiple inventors who share the name “KIM KYU-HYOUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM KYU-HYOUN

IBM

Concurrent upgrade and backup of non-volatile memory

Selective memory error reporting

Advanced memory device having reduced power and improved performance

Providing a memory device having a shared error feedback pin

System for generating a multiple phase clock

Synchronous memory having shared CRC and strobe pin

System for providing open-loop quadrature clock generation

Error correction potency improvement via added burst beats in a dram access cycle

Error monitoring of a memory device containing embedded error correction

Concurrent upgrade and backup of non-volatile memory

Error monitoring of a memory device containing embedded error correction

Memory system connector

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

Implementing decoupling devices inside a TSV DRAM stack

Implementing multiple different types of dies for memory stacking

SAMSUNG ELECTRONICS CO LTD

Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same

Integrated circuit devices having duty cycle correction circuits that receive control signals over first and second separate paths and methods of operating the same

Semiconductor memory device having duty cycle correction circuit and interpolation circuit interpolating clock signal in the semiconductor memory device

Charge pump circuit

Methods and circuits for correcting a duty-cycle of a signal

Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same

Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals

Semiconductor memory device post-repair circuit and method

Semiconductor memory device having partially controlled delay locked loop

Delay locked loop circuit having duty cycle correction function and delay locking method

Input buffer circuits with input signal boost capability and methods of operation thereof

Delay-locked loop circuit having master-slave structure

Delay locked loop circuit and method for generating internal clock signal

Semiconductor driver circuit with signal swing balance and enhanced testing

Data input and data output control device and method

Phase locked loop circuit and method of locking a phase

FOSTER SR JIMMY G

Integrated circuit die stacks with rotationally symmetric vias

Integrated circuit die stacks with translationally compatible vias

Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same

Integrated circuit die stacks with translationally compatible vias

Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Duty cycle distortion correction

Advanced memory device having improved performance, reduced power and increased reliability

COTEUS PAUL W

Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device

Memory device refresh

SAMUSNG ELECTRONICS CO LTD

Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information

HENDERSON JOAB D

Implementing decoupling devices inside a TSV DRAM stack

SAMSUNG ELCTRONICS CO LTD

Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof

MAULE WARREN EDWARD

Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

GLOBALFOUNDRIES INC

Memory system for mirroring data

FRANCESCHINI MICHELE M

Method for optimizing refresh rate for DRAM

CHUNG HOE-JU

Method of detecting error in a semiconductor memory device