Inventor

COTEUS PAUL W

US180 patents

⚠️ This page may combine multiple inventors who share the name “COTEUS PAUL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COTEUS PAUL W

IBM

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Massively parallel supercomputer

Radio frequency circuit and memory in thin flexible package

Method and apparatus of water cooling several parallel circuit cards each containing several chip packages

Collective network for computer structures

Method and apparatus for cooling an equipment enclosure through closed-loop, liquid-assisted air cooling in combination with direct liquid cooling

Optimized scalable network switch

Secure viewing of display units using a wavelength filter

Ultrascalable petaflop parallel supercomputer

Method and apparatus for cooling an equipment enclosure through closed-loop liquid-assisted air cooling in combination with direct liquid cooling

Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Apparatus and method for inspection and alignment of semiconductor chips and conductive lead frames

Method of operatively combining a plurality of components to form a land grip array interposer (LGA) structure utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Method of operatively combining a plurality of components to form a land grip array interposer (LGA) structure utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Method of forming a land grid array (LGA) interposer arrangement utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Method of forming a land grid array interposer

Land grid array (LGA) interposer structure of a moldable dielectric polymer providing for electrical contacts on opposite sides of a carrier plane

Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries

Circuit and method for reading data transfers that are sent with a source synchronous clock signal

Secure viewing of display units using an electronic shutter

Removable heat sink assembly for a chip package

Clock distribution network

Secure viewing of display units by image superposition and wavelength separation

Packages for stacked integrated circuit chip cubes

Multi-chip module

Flexible cold plate with enhanced flexibility

Advanced memory device having reduced power and improved performance

Providing a memory device having a shared error feedback pin

Method of producing a land grid array interposer structure

Coined-sheet-metal heatsinks for closely packaged heat-producing devices such as dual in-line memory modules (DIMMs)

System for generating a multiple phase clock

Synchronous memory having shared CRC and strobe pin

System for providing open-loop quadrature clock generation

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Fault isolation through no-overhead link level CRC

Optical system for the projection of patterned light onto the surfaces of three dimensional objects

High density, high performance memory circuit package

Low latency memory access and synchronization

Global tree network for computing structures enabling global processing operations

BLUMRICH MATTHIAS A

Collective network for computer structures

Massively parallel supercomputer

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

INTERMEC IP CORP

RFID integrated in electronic assets

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

COTEUS PAUL W

Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

CIPOLLA THOMAS M

Apparatus and method of direct water cooling several parallel circuit cards each containing several chip packages