Inventor

Shen Dongna

US62 patents

⚠️ This page may combine multiple inventors who share the name “Shen Dongna”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Shen Dongna

TAIWAN SEMICONDUCTOR MFG CO LTD

Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

Under-cut via electrode for sub 60 nm etchless MRAM devices by decoupling the via etch process

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive R-deposition

Highly selective ion beam etch hard mask for sub 60nm MRAM devices

Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

Multiple spacer assisted physical etching of sub 60nm MRAM devices

Highly selective ion beam etch hard mask for sub 60nm MRAM devices

Post treatment to reduce shunting devices for physical etching process

MTJ CD variation by HM trimming

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive R-deposition

Multiple spacer assisted physical etching of sub 60nm MRAM devices

Highly physical ion resistive spacer to define chemical damage free sub 60nm MRAM devices

Self-adaptive halogen treatment to improve photoresist pattern and magnetoresistive random access memory (MRAM) device uniformity

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Multiple spacer assisted physical etching of sub 60nm MRAM devices

MTJ CD variation by HM trimming

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

Combined physical and chemical etch to reduce magnetic tunnel junction (MTJ) sidewall damage

Self-adaptive halogen treatment to improve photoresist pattern and magnetoresistive random access memory (MRAM) device uniformity

Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

Highly physical ion resistive spacer to define chemical damage free sub 60nm MRAM devices

Highly physical etch resistive photoresist mask to define large height sub 30nm via and metal hard mask for MRAM devices

Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

Highly physical ion resistive spacer to define chemical damage free sub 60 nm MRAM devices

Sub 60nm etchless MRAM devices by ion beam etching fabricated t-shaped bottom electrode

Large height tree-like sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices

Highly selective ion beam etch hard mask for sub 60nm MRAM devices

Highly physical etch resistive photoresist mask to define large height sub 30nm via and metal hard mask for MRAM devices

Large height tree-like sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

Post treatment to reduce shunting devices for physical etching process

HEADWAY TECH INC

Etch selectivity by introducing oxidants to noble gas during physical magnetic tunnel junction (MTJ) etching

Free layer sidewall oxidation and spacer assisted magnetic tunnel junction (MTJ) etch for high performance magnetoresistive random access memory (MRAM) devices

MTJ device process/integration method with pre-patterned seed layer

Dielectric encapsulation layer for magnetic tunnel junction (MTJ) devices using radio frequency (RF) sputtering

Spacer assisted ion beam etching of spin torque magnetic random access memory

Hybrid metallic hard mask stack for MTJ etching

Ion beam etching process design to minimize sidewall re-deposition

Reduce intermixing on MTJ sidewall by oxidation

Magnetic tunnel junction (MTJ) performance by introducing oxidants to methanol with or without noble gas during MTJ etch

High temperature volatilization of sidewall materials from patterned magnetic tunnel junctions

MTJ etching with improved uniformity and profile by adding passivation step

Method to minimize MTJ sidewall damage and bottom electrode redeposition using IBE trimming

Etching and encapsulation scheme for magnetic tunnel junction fabrication