Inventor

QAWAMI SHEKOUFEH

US67 patents

⚠️ This page may combine multiple inventors who share the name “QAWAMI SHEKOUFEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QAWAMI SHEKOUFEH

INTEL CORP

Method and apparatus for senior loads

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Interface for storage device access over memory bus

Method and apparatus for load buffers

Flexible DLL (delay locked loop) calibration

Reduced uncorrectable memory errors

Multi-level memory with direct access

Managing threshold voltage shift in nonvolatile memory

Reduced uncorrectable memory errors

Command-based control of NAND flash memory

Dual use for data valid signal in non-volatile memory

Configuring levels of program/erase protection in flash devices

Methods and apparatus to train interdependent autonomous machines

Flexible selection command for non-volatile memory

Flexible DLL (delay locked loop) calibration

Adaptive configuration of non-volatile memory

Interface for storage device access over memory bus

Reduced uncorrectable memory errors

Method and system to retrieve information

Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence

Evaluating risk factors of proposed vehicle maneuvers using external and internal data

Failure indicator predictor (FIP)

Auto-increment write count for nonvolatile memory

Scalable bandwidth non-volatile memory

Multi-level memory with direct access

Multi-level memory with direct access

High speed fanned out system architecture and input/output circuits for non-volatile memory

Use of flash memory blocks outside of the main flash memory array

Methods and apparatus to add common sense reasoning to artificial intelligence in the context of human machine interfaces

MICRON TECHNOLOGY INC

Memory access techniques in memory devices with multiple partitions

Writing to non-volatile memory during a volatile memory refresh cycle

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Memory access techniques in memory devices with multiple partitions

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Apparatuses and methods for adjusting write parameters based on a write count

Memory access techniques in memory devices with multiple partitions

Apparatuses and methods for adjusting write parameters based on a write count

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Phase change memory in a dual inline memory module

PALANCA SALVADOR

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Method and system for accessing memory in parallel computing using load fencing instructions

QAWAMI SHEKOUFEH

Interface for storage device access over memory bus

Method, apparatus and system for determining an identifier of a volume of memory

Phase change memory in a dual inline memory module

Flexible selection command for non-volatile memory

FANNING BLAISE

Multi-level memory with direct access