Inventor

KIMELMAN PAUL

US44 patents

⚠️ This page may combine multiple inventors who share the name “KIMELMAN PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIMELMAN PAUL

ADVANCED RISC MACH LTD

Breakpoint logic unit, debug logic and breakpoint method for a data processing apparatus

On-board diagnostic circuit for an integrated circuit

Communication interface for diagnostic circuits of an integrated circuit

Diagnostic data capture within an integrated circuit

Communication interface for diagnostic circuits of an integrated circuit

Data processing apparatus having memory protection unit

Cross-triggering of processing devices

Management of polling loops in a data processing apparatus

Diagnostic mechanisms within multi processing systems

Forced diagnostic entry upon power-up

Selecting subroutine return mechanisms

Method and apparatus for using a RAM memory block to remap ROM access requests

Interrupt priority control within a nested interrupt system

Access to bit values within data words stored in a memory

Interrupt pre-emption and ordering within a data processing system

Interrupt controller and method for handling interrupts

Performing diagnostic operations upon a data processing apparatus with power down support

Diagnostic mode switching

Diagnostic mode switching

Interrupt processing control

Controlling complex non-linear data transfers

Stack memory selection upon exception in a data processing system

TEXAS INSTRUMENTS INC

Power efficient method for Wi-Fi home automation

Capacitive sensing

Capacitive sensing

Circuits and methods for determining the temperature of a transistor

Capacitive sensing

Capacitive sensing

Capacitive sensing

Integrated gearbox/encoder and control system

NXP USA INC

Data processing system having a shared cache

Glitch detection in input/output bus

Producer/consumer paced data transfer within a data processing system having a cache which implements different cache coherency protocols

Scalable neural network accelerator architecture

Data processing system implemented having a distributed cache

Cache pre-loading in a data processing system

KIMELMAN PAUL

Microcontroller with embedded secure feature

Multi-core processing utilizing prioritized interrupts for optimization

Effective mixing real-time software with a non-real-time operating system

Security intrusion detection and response

Controlling complex non-linear data transfers

MICROTEC RESEARCH INC

Method and apparatus for statement level debugging of a computer program

NXP BV

Systems and methods for detection of persistent faults in processing units and memory

AXFORD SIMON

Multi-region default memory map