Inventor

CULLEY PAUL R

US64 patents

⚠️ This page may combine multiple inventors who share the name “CULLEY PAUL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CULLEY PAUL R

COMPAQ COMPUTER CORP

Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Computer diagnostic board that provides system monitoring and permits remote terminal access

Computer system bus performance monitoring

System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal

Method and apparatus for identifying faulty devices in a computer system

Data error detection and correction

Synchronizing data between devices

Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems

Delaying arbitration of bus access in digital computers

Computer system speed control at continuous processor speed

System for fast selection of non-cacheable address ranges using programmed array logic

Personal computer having normal and high speed execution modes

Priority arbitration circuit for processor access

Method and apparatus for diagnosing fault states in a computer system

Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system

Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew

Double buffering operations between the memory bus and the expansion bus of a computer system

Providing data from a bridge to a requesting device while the bridge is receiving the data

Double buffering operations between the memory bus and the expansion bus of a computer system

Double buffering operations between the memory bus and the expansion bus of a computer system

Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration

Paged memory controller

Enhanced locked bus cycle control in a cache memory computer system

Computer system with high speed data transfer capabilities

System for fast selection of non-cacheable address ranges using programmed array logic

System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory

Programmable interrupt controller

Personal computer having normal and high speed execution modes

Multi-processor system with system wide reset and partial system reset capabilities

Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits

Apparatus for strictly ordered input/output operations for interrupt system integrity

Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals

Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes

Expansion card insertion and removal

Removal and insertion of expansion cards in a computer system

Bus arbitration

Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems

Extended duration high resolution timer contained in two integrated circuits and having alternating data sequences provided from different integrated circuits

System for controlling the transferring of different widths of data using two different sets of address control signals

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for implementing work request lists

Binding a memory window to a queue pair

Method and apparatus for accessing a memory

Memory window access mechanism

TEXAS INSTRUMENTS INC

Pulse width modulation of printhead voltage

Video display controller system with attribute latch

KRAUSE MICHAEL R

Reliable datagram transport service

COMPAQ COMP CORP INC

Processor based system with system wide reset and partial system reset capabilities

(unassigned)

Storing data associated with one request while continuing to store data associated with a previous request from the same device