Inventor

MANNING MONTE

US157 patents

⚠️ This page may combine multiple inventors who share the name “MANNING MONTE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANNING MONTE

MICRON TECHNOLOGY INC

Thin film transistors

Fully planarized thin film transistor (TFT) and process to fabricate same

Redundancy elements using thin film transistors (TFTs)

Trench isolation method having a double polysilicon gate formed on mesas

MOS diode for use in a non-volatile memory cell background

Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors

Static memory cell

MOS diode for use in a non-volatile memory cell

SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making

Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer

Semiconductor processing methods of forming field oxide regions on a semiconductor substrate

Integrated circuitry having a pair of adjacent conductive lines

SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making

Redundancy elements using thin film transistors (TFTs)

Method of making a resistor

Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions

Method of forming a planar thin film transistor

Method of making self-aligned vertical intrinsic resistance

Vertically integrated oxygen-implanted polysilicon resistor

Method for forming a multilevel interconnect structure on a semiconductor wafer

Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects

Integrated circuitry and a semiconductor processing method of forming a series of conductive lines

Integrated circuitry conductive lines

Apparatus improving latchup immunity in a dual-polysilicon gate

Static memory cell

Static memory cell

Methods of forming conductive lines

Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry

SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making

Static memory cell

Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS

Planar thin film transistor structures

Apparatus for improving latchup immunity in a dual polysilicon gate process

Semiconductor processing method of forming a buried contact

Semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate

Method of forming a thin film transistor

Semiconductor processing method of forming a buried contact and conductive line

Integrated circuitry having a pair of adjacent conductive lines and method of forming

Method for forming and tailoring the electrical characteristics of semiconductor devices

Methods of forming conductive polysilicon lines and bottom gated thin film transistors

Thin film transistor redundancy structure

MICRON SEMICONDUCTOR INC

Trench isolation using gated sidewalls

Sixteen megabit static random access memory (SRAM) cell

Method for improving latchup immunity in a dual-polysilicon gate process

Non-volatile static memory devices and operational methods

Method of forming a self-aligned low density drain inverted thin film transistor

Thin film transistor (TFT) loads formed in recessed plugs

Self-aligned low resistance buried contact process

Method of forming improved contacts from polysilicon to silicon or other polysilicon layers

MICRON TEHNOLOGY INC

Methods of making a SRAM cell employing substantially vertically elongated pull-up resistors and methods of making resistor constructions