Inventor

DENNISON CHARLES

US41 patents

⚠️ This page may combine multiple inventors who share the name “DENNISON CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DENNISON CHARLES

MICRON TECHNOLOGY INC

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls

Array of bit line over capacitor array of memory cells

Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Method of forming a bit line over capacitor array of memory cells

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Graded LDD implant process for sub-half-micron MOS devices

Capacitor structures for dynamic random access memory cells

Method of forming a planar thin film transistor

Method of forming a buried bit line array of memory cells

Graded LDD implant process for sub-half-micron MOS devices

Semiconductor memory having dual port cell supporting hidden refresh

Graded LDD implant process for sub-half-micron MOS devices

Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate

Planar thin film transistor structures

Method for forming and tailoring the electrical characteristics of semiconductor devices

Method for forming and tailoring the electrical characteristics of semiconductor devices

Method for forming self-aligned conducting pillars in an (IC) fabrication process

Graded LDD implant process for sub-half-micron MOS devices

Graded LDD implant process for sub-half-micron MOS devices

Semiconductor memory having dual port cell supporting hidden refresh

Graded LDD implant process for sub-half-micron MOS devices

Graded LDD implant process for sub-half-micron MOS devices

Planar thin film transistor structures

Capacitor structures for memory cells

OVONYX INC

Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory

Lower electrode isolation in a double-wide trench

Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact

Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact

Forming phase change memories

Forming phase change memories

Lower electrode isolation in a double-wide trench and method of making same

Forming phase change memories

Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby

Multilevel variable resistance memory cell utilizing crystalline programming states

INTEL CORP

Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby

Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby

Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby

Semiconductor photonic devices using phase change materials

ST MICROELECTRONICS SRL

Shared address lines for crosspoint memory