Inventor
KHANDEKAR NARENDRA
US12 patents
Patents
12 patentsUS6567904B1May 20, 2003
Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
INTEL CORP74 citations95
US5802603ASep 1, 1998
Method and apparatus for asymmetric/symmetric DRAM detection
INTEL CORP20 citations92
US5715476AFeb 3, 1998
Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
INTEL CORP39 citations92
US5519872AMay 21, 1996
Fast address latch with automatic address incrementing
INTEL CORP21 citations92
US6049887AApr 11, 2000
Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
INTEL CORP40 citations90
US5961649AOct 5, 1999
Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
INTEL CORP28 citations90
US6112307AAug 29, 2000
Method and apparatus for translating signals between clock domains of different frequencies
INTEL CORP38 citations89
US7000133B2Feb 14, 2006
Method and apparatus for controlling power states in a memory device utilizing state information
INTEL CORP12 citations84
US6202112B1Mar 13, 2001
Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge
INTEL CORP19 citations82
US6154825ANov 28, 2000
Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations
INTEL CORP13 citations73
US5666556ASep 9, 1997
Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
INTEL CORP7 citations73
US6173354B1Jan 9, 2001
Method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus
INTEL CORP6 citations62