Inventor
MERCHANT AMIT A
US20 patents
Patents
20 patentsUS6385715B1May 7, 2002
Multi-threading for a processor utilizing a replay queue
INTEL CORP152 citations99
US5893151AApr 6, 1999
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP124 citations99
US6792446B2Sep 14, 2004
Storing of instructions relating to a stalled thread
INTEL CORP60 citations96
US6785803B1Aug 31, 2004
Processor including replay queue to break livelocks
INTEL CORP55 citations96
US6334182B2Dec 25, 2001
Scheduling operations using a dependency matrix
INTEL CORP69 citations96
US6163838ADec 19, 2000
Computer processor with a replay system
INTEL CORP74 citations96
US6094717AJul 25, 2000
Computer processor with a replay system having a plurality of checkers
INTEL CORP55 citations96
US5890200AMar 30, 1999
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP54 citations96
US5875467AFeb 23, 1999
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP61 citations96
US5778438AJul 7, 1998
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP37 citations96
US5737758AApr 7, 1998
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP32 citations96
US5737759AApr 7, 1998
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
INTEL CORP44 citations96
US7219349B2May 15, 2007
Multi-threading techniques for a processor utilizing a replay queue
INTEL CORP20 citations92
US7200737B1Apr 3, 2007
Processor with a replay system that includes a replay queue for improved throughput
INTEL CORP49 citations92
US6665792B1Dec 16, 2003
Interface to a memory system for a processor having a replay system
INTEL CORP35 citations92
US6212626B1Apr 3, 2001
Computer processor having a checker
INTEL CORP42 citations92
US5909699AJun 1, 1999
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP19 citations92
US5797026AAug 18, 1998
Method and apparatus for self-snooping a bus during a boundary transaction
INTEL CORP41 citations92
US5572702ANov 5, 1996
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP40 citations92
US7089409B2Aug 8, 2006
Interface to a memory system for a processor having a replay system
INTEL CORP7 citations74