Inventor

WEBER FREDERICK D

US32 patents

⚠️ This page may combine multiple inventors who share the name “WEBER FREDERICK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEBER FREDERICK D

ADVANCED MICRO DEVICES INC

System and method for conditional moving an operand from a source register to destination register

Flexible implementation of a system management mode (SMM) in a processor

Computer system with processor cache that stores remote cache presence information

Flexible implementation of a system management mode (SMM) in a processor

Method and apparatus for multi-function arithmetic

Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction

System including a host connected to a plurality of memory modules via a serial memory interconnect

Locking mechanism override and disable for personal computer ROM access protection

Method and apparatus for rounding in a multiplier

Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit

Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values

Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions

External locking mechanism for personal computer memory locations

Secure booting of a personal computer system

Method and apparatus for rapid execution of FCOM and FSTSW

Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria

Computer system including a novel address translation mechanism

Method and apparatus for calculating a power of an operand

COMPAQ COMPUTER CORP

System and method for conditionally moving an operand from a source register to a destination register

Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage

System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot

Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle

Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot

KENDALL SQUARE RESEARCH CORP

Shared memory multiprocessor system and method of operation thereof

Multiprocessor digital data processing system

Register bus multiprocessor system with shift

Shared memory multiprocessor with data hiding and post-store

SUN MICROSYSTEMS INC

Multiprocessor digital data processing system/shared memory multiprocessor system and method of operation

System for inserting instructions into processor instruction stream in order to perform interrupt processing

Multiprocessor digital data processing system

Multiprocessor digital data processing system

COMPAQ COMPUTER CORP AND ADVAN

Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles