Inventor

CHA RANDALL CHER LIANG

SG28 patents

⚠️ This page may combine multiple inventors who share the name “CHA RANDALL CHER LIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHA RANDALL CHER LIANG

CHARTERED SEMICONDUCTOR MFG

Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant

Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

Method to reduce polysilicon depletion in MOS transistors

Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers

Versatile copper-wiring layout design with low-k dielectric integration

Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique

Method of fabricating CMOS device with dual gate electrode

Method to reduce compressive stress in the silicon substrate during silicidation

Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Method to fabricate a single gate with dual work-functions

Forming dual gate oxide thickness on vertical transistors by ion implantation

Method for fabricating complementary silicon on insulator devices using wafer bonding

Dual silicon-on-insulator device wafer die

Simplified method to reduce or eliminate STI oxide divots

Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer

Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer

Method to fabricate elevated source/drain transistor with large area for silicidation

Method to fabricate elevated source/drain structures in MOS transistors

Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

Technique to achieve thick silicide film for ultra-shallow junctions

Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

CHESTNUT SPRINGS LLC

Flame retardant compositions and processes for preparation thereof

Method for imparting flame retardancy to a substrate material

Process for preparing flame retardant compositions

CHARTERED SEMICONDUCTORS MAUFA

Dual silicon-on-insulator device wafer die

CHARTERED SEMICONDUCTOR MANFAC

Integrated circuit with self-aligned line and via and manufacturing method therefor

LIM YEOW KHENG

Integrated circuit with self-aligned line and via