Inventor

BUEHLER MARKUS

CH27 patents

⚠️ This page may combine multiple inventors who share the name “BUEHLER MARKUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUEHLER MARKUS

IBM

Test yield estimate for semiconductor products created from a library

Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

Method and system for placement of electric circuit components in integrated circuit design

Computer readable medium, system and associated method for designing integrated circuits with loop insertions

Test yield estimate for semiconductor products created from a library

Partial computer processor core shutoff

Routing of wires of an electronic circuit

Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing

Congestion mitigation by wire ordering

Multitasking scheme for quantum computers

Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit

Reducing coupling between wires of an electronic circuit

Flexible synchronization of time-of-day components

Central controller for a quantum system

Parsing data representative of a hardware design into commands of a hardware design environment

Hardware apparatus to measure memory locality

BUECHNER THOMAS

Glitch power reduction

Gate configuration determination and selection from standard cell library

Estimating power consumption of an electronic circuit

BUEHLER MARKUS

Signal repowering chip for 3-dimensional integrated circuit

Method and system for calculating timing delay in a repeater network in an electronic circuit

SCIENT X SOC A RESPONSABILITE

Disk prosthesis for cervical vertebrae

SCIENT X SA

Disk prosthesis for cervical vertebrae

ANDERSON BRENT A

Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same

BALKESEN CAGRI

Write buffer for improved DRAM write access patterns

NISTOR ALECSANDRU

Radiometric fill level measuring arrangement