Inventor
NASSIF NEVINE
US14 patents
⚠️ This page may combine multiple inventors who share the name “NASSIF NEVINE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
7 patentsUS10795853B2Oct 6, 2020
Multiple dies hardware processors and methods
INTEL CORP9 citations82
US11586579B2Feb 21, 2023
Multiple dies hardware processors and methods
INTEL CORP2 citations71
US11899615B2Feb 13, 2024
Multiple dies hardware processors and methods
INTEL CORP0 citations61
US11294852B2Apr 5, 2022
Multiple dies hardware processors and methods
INTEL CORP0 citations61
US12599033B2Apr 7, 2026
Quasi-monolithic integrated packaging architecture with mid-die serializer/deserializer
INTEL CORP0 citations60
US12469820B2Nov 11, 2025
Fine-grained disaggregated server architecture
INTEL CORP0 citations51
US11127712B2Sep 21, 2021
Functionally redundant semiconductor dies and package
INTEL CORP0 citations47
HEWLETT PACKARD DEVELOPMENT CO
3 patentsUS6654713B1Nov 25, 2003
Method to compress a piecewise linear waveform so compression error occurs on only one side of the waveform
HEWLETT PACKARD DEVELOPMENT CO29 citations89
US6606587B1Aug 12, 2003
Method and apparatus for estimating elmore delays within circuit designs
HEWLETT PACKARD DEVELOPMENT CO10 citations68
US6877142B2Apr 5, 2005
Timing verifier for MOS devices and related method
HEWLETT PACKARD DEVELOPMENT CO0 citations47
COMPAQ COMPUTER CORP
3 patentsUS6473888B1Oct 29, 2002
Timing verifier for MOS devices and related method
COMPAQ COMPUTER CORP4 citations58
US6658506B1Dec 2, 2003
Method and apparatus for performing timing verification of a circuit
COMPAQ COMPUTER CORP4 citations56
US6438732B1Aug 20, 2002
Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)
COMPAQ COMPUTER CORP0 citations36