Inventor

IACOBOVICI SORIN

US32 patents

⚠️ This page may combine multiple inventors who share the name “IACOBOVICI SORIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IACOBOVICI SORIN

SUN MICROSYSTEMS INC

Versatile register file design for a multi-threaded processor utilizing different modes and register windows

Multi-stride prefetcher with a recurring prefetch table

End-to-end residue based protection of an execution pipeline

Handling register dependencies between instructions specifying different width registers

Microprocessor speed control mechanism using power dissipation estimation based on the instruction data path

Techniques for reducing off-chip cache memory accesses

Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream

Residue-based error detection for a shift operation

Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor

Method and apparatus for processing a complex instruction for execution and retirement

Register window flattening logic for dependency checking among instructions

Register window spill technique for retirement window having entry size less than amount of spill instructions

Method and apparatus for protecting a state associated with a memory structure

Vector technique for addressing helper instruction groups associated with complex instructions

Register window fill technique for retirement window having entry size less than amount of fill instructions

INTEL CORP

Saving and restoring architectural state for processor cores

Residue based error detection for integer and floating point execution units

In-field system test security

Consecutive bit error detection and correction

Method and apparatus for handling data errors in a computer system

In-field system testing

HEWLETT PACKARD CO

Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss

Forming linked lists using content addressable memory

Conflict cache having cache miscounters for a computer memory system

Apparatus and method using a semaphore buffer for semaphore instructions

Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations

INST THE DEV OF EMERGING ARCHI

Cache arrangement including coalescing buffer queue for non-cacheable data

Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues

HEWLETT PACKARD DEVELOPMENT CO

Forming linked lists using content addressable memory

NAT SEMICONDUCTOR CORP

Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits

MUNOZ ALBERTO J

Core sparing on multi-core platforms

ORACLE AMERICA INC

End-to-end residue-based protection of an execution pipeline that supports floating point operations