Inventor
KIMBALL JAMES
US14 patents
⚠️ This page may combine multiple inventors who share the name “KIMBALL JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
13 patentsUS6087229AJul 11, 2000
Composite semiconductor gate dielectrics
LSI LOGIC CORP180 citations99
US6033998AMar 7, 2000
Method of forming variable thickness gate dielectrics
LSI LOGIC CORP96 citations98
US5963801AOct 5, 1999
Method of forming retrograde well structures and punch-through barriers using low energy implants
LSI LOGIC CORP60 citations94
US5904551AMay 18, 1999
Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells
LSI LOGIC CORP28 citations92
US5739580AApr 14, 1998
Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation
LSI LOGIC CORP17 citations92
US5707888AJan 13, 1998
Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation
LSI LOGIC CORP21 citations92
US5654210AAug 5, 1997
Process for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrate
LSI LOGIC CORP28 citations92
US5585286ADec 17, 1996
Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device
LSI LOGIC CORP39 citations91
US6180470B1Jan 30, 2001
FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
LSI LOGIC CORP15 citations82
US5858864AJan 12, 1999
Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate
LSI LOGIC CORP11 citations74
US5717238AFeb 10, 1998
Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
LSI LOGIC CORP8 citations72
US7323228B1Jan 29, 2008
Method of vaporizing and ionizing metals for use in semiconductor processing
LSI LOGIC CORP3 citations63
US7084408B1Aug 1, 2006
Vaporization and ionization of metals for use in semiconductor processing
LSI LOGIC CORP5 citations63