Inventor
SUKHAREV VALERIY
US20 patents
⚠️ This page may combine multiple inventors who share the name “SUKHAREV VALERIY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
14 patentsUS6087229AJul 11, 2000
Composite semiconductor gate dielectrics
LSI LOGIC CORP180 citations99
US6033998AMar 7, 2000
Method of forming variable thickness gate dielectrics
LSI LOGIC CORP96 citations98
US7138292B2Nov 21, 2006
Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide
LSI LOGIC CORP76 citations97
US6303047B1Oct 16, 2001
Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same
LSI LOGIC CORP81 citations96
US6147012ANov 14, 2000
Process for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constant
LSI LOGIC CORP52 citations96
US6114259ASep 5, 2000
Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
LSI LOGIC CORP218 citations95
US5837598ANov 17, 1998
Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same
LSI LOGIC CORP91 citations94
US6524974B1Feb 25, 2003
Formation of improved low dielectric constant carbon-containing silicon oxide dielectric material by reaction of carbon-containing silane with oxidizing agent in the presence of one or more reaction retardants
LSI LOGIC CORP26 citations92
US6365528B1Apr 2, 2002
Low temperature process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric-material characterized by improved resistance to oxidation and good gap-filling capabilities
LSI LOGIC CORP35 citations92
US6506678B1Jan 14, 2003
Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same
LSI LOGIC CORP15 citations84
US6777807B1Aug 17, 2004
Interconnect integration
LSI LOGIC CORP7 citations73
US6759337B1Jul 6, 2004
Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate
LSI LOGIC CORP3 citations61
US6935933B1Aug 30, 2005
Viscous electropolishing system
LSI LOGIC CORP0 citations42
US6426286B1Jul 30, 2002
Interconnection system with lateral barrier layer
LSI LOGIC CORP0 citations41
MENTOR GRAPHICS CORP
5 patentsUS9135391B2Sep 15, 2015
Determination of electromigration susceptibility based on hydrostatic stress analysis
MENTOR GRAPHICS CORP2 citations61
US7687303B1Mar 30, 2010
Method for determining via/contact pattern density effect in via/contact etch rate
MENTOR GRAPHICS CORP6 citations61
US10013523B2Jul 3, 2018
Full-chip assessment of time-dependent dielectric breakdown
MENTOR GRAPHICS CORP0 citations52
US9836569B2Dec 5, 2017
Leakage reduction using stress-enhancing filler cells
MENTOR GRAPHICS CORP0 citations40
US9740804B2Aug 22, 2017
Chip-scale electrothermal analysis
MENTOR GRAPHICS CORP1 citations40