Inventor

LAU BENEDICT C

US48 patents

⚠️ This page may combine multiple inventors who share the name “LAU BENEDICT C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAU BENEDICT C

RAMBUS INC

System with phase jumping locked loop circuit

Delay locked loop circuitry for clock delay adjustment

Apparatus and method for generating multiple clock signals from a single loop circuit

Delay-locked loop circuitry for clock delay adjustment

Method and apparatus for low capacitance, high output impedance driver

Differential amplifiers with current and resistance compensation elements for balanced output

Memory controller with staggered request signal output

Memory controller with staggered request signal output

System with dual rail regulated locked loop

Delay locked loop circuitry for clock delay adjustment

Locked loop with dual rail regulation

System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively

System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers

Scalable I/O signaling topology using source-calibrated reference voltages

Signaling accommodation

Locked loop with dual rail regulation

System with dual rail regulated locked loop

Signaling accommodation

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Delay locked loop circuitry for clock delay adjustment

Phase jumping locked loop circuit

System with phase jumping locked loop circuit

Collective automatic gain control

Collective automatic gain control

Method and apparatus for low capacitance, high output impedance driver

Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback

Memory controller with staggered request signal output

Memory device with circuitry to transmit feedback indicative of a phase relationship

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Memory controller with staggered request signal output

Method and apparatus for programmable sampling clock edge selection

Phase synchronization for wide area integrated circuits

Method and apparatus for low capacitance, high output impedance driver

Apparatus and method for generating clock signals

Phase synchronization for wide area integrated circuits

Apparatus and method for generating clock signals

Differential amplifier with selectable hysteresis and buffered filter

Memory controller with staggered request signal output

Collective automatic gain control

Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback

Phase synchronization for wide area integrated circuits

Method and apparatus for low capacitance, high output impedance driver

SHAEFFER IAN P

Memory controller with staggered request signal output

Integrated circuit with staggered signal output

RAMBUS

Differential amplifier with selectable hysteresis and buffered filter