Inventor
CHAN YIU-FAI
US15 patents
⚠️ This page may combine multiple inventors who share the name “CHAN YIU-FAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
8 patentsUS4774421ASep 27, 1988
Programmable logic array device using EPROM technology
ALTERA CORP194 citations98
US4617479AOct 14, 1986
Programmable logic array device using EPROM technology
ALTERA CORP361 citations98
US5111423AMay 5, 1992
Programmable interface for computer system peripheral circuit card
ALTERA CORP243 citations97
US4713792ADec 15, 1987
Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits
ALTERA CORP257 citations97
US4609986ASep 2, 1986
Programmable logic array device using EPROM technology
ALTERA CORP442 citations96
US4969121ANov 6, 1990
Programmable integrated circuit logic array device having improved microprocessor connectability
ALTERA CORP55 citations91
US4930107AMay 29, 1990
Method and apparatus for programming and verifying programmable elements in programmable devices
ALTERA CORP51 citations91
US5066873ANov 19, 1991
Integrated circuits with reduced switching noise
ALTERA CORP41 citations89
RAMBUS INC
6 patentsUS6539072B1Mar 25, 2003
Delay locked loop circuitry for clock delay adjustment
RAMBUS INC263 citations99
US6125157ASep 26, 2000
Delay-locked loop circuitry for clock delay adjustment
RAMBUS INC382 citations99
US5945862AAug 31, 1999
Circuitry for the delay adjustment of a clock signal
RAMBUS INC152 citations99
US7039147B2May 2, 2006
Delay locked loop circuitry for clock delay adjustment
RAMBUS INC34 citations96
US6047346AApr 4, 2000
System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
RAMBUS INC268 citations96
US7308065B2Dec 11, 2007
Delay locked loop circuitry for clock delay adjustment
RAMBUS INC15 citations92