Inventor
LE HIEN MINH
US20 patents
⚠️ This page may combine multiple inventors who share the name “LE HIEN MINH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS9336142B2May 10, 2016
Cache configured to log addresses of high-availability data via a non-blocking channel
IBM9 citations83
US7080269B2Jul 18, 2006
Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
IBM20 citations82
US7716546B2May 11, 2010
System and method for improved LBIST power and run time
IBM11 citations79
US7409469B2Aug 5, 2008
Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted
IBM5 citations71
US7836257B2Nov 16, 2010
System and method for cache line replacement selection in a multiprocessor environment
IBM3 citations60
US9529717B2Dec 27, 2016
Preserving an invalid global domain indication when installing a shared cache line in a cache
IBM0 citations52
US9483403B2Nov 1, 2016
Techniques for preserving an invalid global domain indication when installing a shared cache line in a cache
IBM0 citations52
US9792208B2Oct 17, 2017
Techniques for logging addresses of high-availability data via a non-blocking channel
IBM0 citations51
US9471491B2Oct 18, 2016
Cache configured to log addresses of high-availability data
IBM0 citations51
US9430382B2Aug 30, 2016
Logging addresses of high-availability data
IBM0 citations51
US8020058B2Sep 13, 2011
Multi-chip digital system having a plurality of controllers with self-identifying signal
IBM1 citations50
APPLIED MATERIALS INC
3 patentsUS7967913B2Jun 28, 2011
Remote plasma clean process with cycled high and low pressure clean steps
APPLIED MATERIALS INC477 citations98
US10410869B2Sep 10, 2019
CVD based oxide-metal multi structure for 3D NAND memory devices
APPLIED MATERIALS INC8 citations84
US11817320B2Nov 14, 2023
CVD based oxide-metal multi structure for 3D NAND memory devices
APPLIED MATERIALS INC0 citations62
GLOBALFOUNDRIES INC
2 patentsUS9280465B2Mar 8, 2016
Techniques for moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache
GLOBALFOUNDRIES INC2 citations63
US9274952B2Mar 1, 2016
Moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache
GLOBALFOUNDRIES INC0 citations52
QUALCOMM INC
2 patentsUS9990291B2Jun 5, 2018
Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols
QUALCOMM INC0 citations48
US9921962B2Mar 20, 2018
Maintaining cache coherency using conditional intervention among multiple master devices
QUALCOMM INC0 citations37