Inventor

BOTHRA SUBHAS

US90 patents

⚠️ This page may combine multiple inventors who share the name “BOTHRA SUBHAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOTHRA SUBHAS

VLSI TECHNOLOGY INC

Micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system

Low power programmable fuse structures

Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection

Methods and apparatus for polishing wafers

Low power programmable fuse structures and methods for making the same

Integrated circuit structure having an air dielectric and dielectric support pillars

Programmable semiconductor structures and methods for making the same

Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die

Automated design of on-chip capacitive structures for suppressing inductive noise

Method for producing deep submicron interconnect vias

Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Methods for making semiconductor devices having air dielectric interconnect structures

Methods for making shallow trench capacitive structures

Method of forming a via hole structure including CVD tungsten silicide barrier layer

Reliable interconnect via structures and methods for making the same

Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device

Reliable interconnect via structures and methods for making the same

Method of making high resistive structures in salicided process semiconductor devices

Methods of forming a semiconductor device

Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same

Apparatus for automated pillar layout and method for implementing same

Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing

Process for manufacturing ultra-sharp atomic force microscope (AFM) and scanning tunneling microscope (STM) tips

Semiconductor pressure transducer structures and methods for making the same

Method for making devices having thin load structures

Method for improving the manufacturability of the spin-on glass etchback process

Method of making microscope probe tips

PHILIPS ELECTRONICS NA

Method for determining nitrogen concentration in a film of nitrided oxide material

Air gap dielectric in self-aligned via structures

Design level optical proximity correction methods

Methods for forming co-axial interconnect lines in a CMOS process for high speed applications

Methods and apparatus for design rule checking

Intelligent gate-level fill methods for reducing global pattern density effects

Reliable aluminum interconnect via structures

Fabrication of gate and diffusion contacts in self-aligned contact process

Electromigration bonding process and system

Semiconductor manufacturing apparatus and method for measuring in-situ pressure across a wafer

Methods for fabricating gate and diffusion contacts in self-aligned contact processes

Programmable integrated circuit structures and methods for making the same

Semiconductor structures for suppressing gate oxide plasma charging damage and methods for making the same

Method for forming aligned vias under trenches in a dual damascene process

Process for making self-aligned conductive via structures

Automated design of on-chip capacitive structures for suppressing inductive noise

Method of making photo alignment structure

ZEEVO INC

Seal ring structure for IC containing integrated digital/RF/analog circuits and functions

Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit

KONINKL PHILIPS ELECTRONICS NV

Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications

PHILIPS ELECTRONICS NO AMERICA

Method for reducing the capacitance between interconnects by forming voids in dielectric material

PHILLIPS ELECTRONICS NORTH AME

Waveguide structures integrated with standard CMOS circuitry and methods for making the same

BROADCOM CORP

Fully differential, high Q, on-chip, impedance matching section