Inventor

HU YONGJUN JEFF

US159 patents

⚠️ This page may combine multiple inventors who share the name “HU YONGJUN JEFF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU YONGJUN JEFF

MICRON TECHNOLOGY INC

Metal silicidation methods and methods for using same

Forming a conductive structure in a semiconductor device

Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer

Manufacture and cleaning of a semiconductor

Gate stack structure with conductive silicide segment that has substantially etched nitride and/or oxynitride defects protruding from its sidewalls

Method of fabricating a wordline in a memory array of a semiconductor device

Forming a conductive structure in a semiconductor device

Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor

Asymmetric, double-sided self-aligned silicide and method of forming the same

Method and composition for selectively etching against cobalt silicide

Resistive memory elements including buffer materials, and related memory cells, memory devices, electronic systems

Methods of forming NAND cell units

Manufacture and cleaning of a semiconductor

Metal gate engineering for surface p-channel devices

Composition for selectively etching against cobalt silicide

Metal gate engineering for surface p-channel devices

Buried bit line memory circuitry

Methods of passivating an oxide surface subjected to a conductive material anneal

Asymmetric, double-sided self-aligned silicide and method of forming the same

Method of fabricating a field effect transistor

Methods of forming a contact to a substrate

Asymmetric, double-sided self-aligned silicide

Method of co-deposition to form ultra-shallow junctions in MOS devices using electroless or electrodeposition

Electrochemical cobalt silicide liner for metal contact fills and damascene processes

Metal silicidation methods and methods for using same

Methods of forming buried bit line memory circuitry

Apparatus and method for forming cold-cathode field emission displays

Method of forming a conductive line and method of forming a local interconnect

Electrochemical cobalt silicide liner for metal contact fills and damascene processes

Semiconductor processing method of forming a high purity &lt;200&gt; grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line

Phase change memory stack with treated sidewalls

Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom

Compound structure for reduced contact resistance

Forming a conductive structure in a semiconductor device

Methods of forming memory cells and memory devices

Phase change memory stack with treated sidewalls

Integrated assemblies and methods of forming integrated assemblies

Source material for electronic device applications

Phase change memory stack with treated sidewalls

Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same

Phase change memory stack with treated sidewalls

Phase change memory stack with treated sidewalls

Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same

Phase change memory stack with treated sidewalls

Phase change memory stack with treated sidewalls

Memory cells having regions containing one or both of carbon and boron

Interconnects and semiconductor devices including at least two portions of a metal nitride material and methods of fabrication

Metal gate engineering for surface P-channel devices

Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon

HU YONGJUN JEFF

Capacitors including at least two portions of a metal nitride material, methods of forming such structures, and semiconductor devices including such structures

Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line