Inventor

CHENG KANGGUO

US2,853 patents

⚠️ This page may combine multiple inventors who share the name “CHENG KANGGUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHENG KANGGUO

IBM

Air gap spacer formation for nano-scale semiconductor devices

Buffer regions for blocking unwanted diffusion in nanosheet transistors

Vertical field-effect transistor with uniform bottom spacer

High density nanosheet diodes

Stacked complementary FETs featuring vertically stacked horizontal nanowires

Stacked transistors with different channel widths

Fabrication of nano-sheet transistors with different threshold voltages

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Vertical transistor with air-gap spacer

Nanosheet MOSFET with full-height air-gap spacer

Gate-all-around nanowire MOSFET and method of formation

Integrating standard-gate and extended-gate nanosheet transistors on the same substrate

Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap

Inner spacer for nanosheet transistors

Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain

Air gap spacer formation for nano-scale semiconductor devices

Stacked nanosheet field effect transistor device with substrate isolation

Replacement metal gate structures

Vertical field effect transistor having U-shaped top spacer

Fabrication of a vertical fin field effect transistor having a consistent channel width

Fabrication of vertical field effect transistors with uniform structural profiles

Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance

Fabrication of a vertical fin field effect transistor with reduced dimensional variations

Fabrication of vertical field effect transistor structure with strained channels

Air-gap top spacer and self-aligned metal gate for vertical fets

Closely packed vertical transistors with reduced contact resistance

Transistor with air spacer and self-aligned contact

Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain

Fabrication of vertical field effect transistor structure with controlled gate length

Forming a hybrid channel nanosheet semiconductor structure

Airgap formation between source/drain contacts and gates

Contact formation to 3D monolithic stacked FinFETs

Fabrication of strained vertical P-type field effect transistors by bottom condensation

Vertical transistor having uniform bottom spacers

Replacement III-V or germanium nanowires by unilateral confined epitaxial growth

Multiple gate length vertical field-effect-transistors

Etch stop for airgap protection

Channel-last replacement metal-gate vertical field effect transistor

Method and structure for forming gate contact above active area with trench silicide

MOSFET with asymmetric self-aligned contact

Method and structure of forming controllable unmerged epitaxial material

Vertical transistor with air gap spacers

Dual work function integration for stacked FinFET

Self-aligned contacts for vertical field effect transistors

Method and structure for improving finFET with epitaxy source/drain

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

Gate-all-around nanowire MOSFET and method of formation

GLOBALFOUNDRIES INC

Nanosheet field-effect transistors including a two-dimensional semiconducting material