Inventor

DORIS BRUCE B

US716 patents

⚠️ This page may combine multiple inventors who share the name “DORIS BRUCE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DORIS BRUCE B

IBM

Nanosheet MOSFET with full-height air-gap spacer

Gate-all-around nanowire MOSFET and method of formation

Metal gated ultra short MOSFET devices

Method for metal gated ultra short MOSFET devices

Ultra thin body fully-depleted SOI MOSFETs

Metal gated ultra short MOSFET devices

High-performance CMOS devices on hybrid crystal oriented substrates

High mobility CMOS circuits

Structure and method to improve channel mobility by gate electrode stress modification

Stress inducing spacers

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device

Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer

Extra gate device for nanosheet

Vertical transistor fabrication and devices

Sidewall image transfer process for fin patterning

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Gate-all-around nanowire MOSFET and method of formation

Dense finFET SRAM

Doping of FinFET structures

High-K/metal gate CMOS finFET with improved pFET threshold voltage

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Strained finFET CMOS device structures

Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs

Hybrid planar and FinFET CMOS devices

Structure and method for manufacturing strained FINFET

Dual gate FinFet

Isolation structures for imposing stress patterns

Method and manufacture of thin silicon on insulator (SOI) with recessed channel

Hybrid planar and finFET CMOS devices

Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer

Structure and method of manufacturing a finFET device having stacked fins

MOS transistor

Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation

CMOS device structure with improved PFET gate electrode

Bulk nanosheet with dielectric isolation

Integrated etch stop for capped gate and method for manufacturing the same

Structure and method to minimize junction capacitance in nano sheets

Strained SiGe nanowire having (111)-oriented sidewalls

Structures and methods for making strained MOSFETs

Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure

Nanosheet MOSFET with full-height air-gap spacer

Nanowire isolation scheme to reduce parasitic capacitance

Nanosheet MOSFET with full-height air-gap spacer

Integrated formation of Si and SiGe fins

FinFET structures having silicon germanium and silicon fins

Inverted thin channel mosfet with self-aligned expanded source/drain

Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

BEDELL STEPHEN W

Strained CMOS device, circuit and method of fabrication

BASKER VEERARAGHAVAN S

High-K/metal gate CMOS finFET with improved pFET threshold voltage