Inventor
WITTIG RALPH D
US54 patents
⚠️ This page may combine multiple inventors who share the name “WITTIG RALPH D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
46 patentsUS6396302B2May 28, 2002
Configurable logic element with expander structures
XILINX INC92 citations99
US6150838ANov 21, 2000
FPGA configurable logic block with multi-purpose logic/memory circuit
XILINX INC315 citations99
US6388466B1May 14, 2002
FPGA logic element with variable-length shift register capability
XILINX INC92 citations98
US6208163B1Mar 27, 2001
FPGA configurable logic block with multi-purpose logic/memory circuit
XILINX INC87 citations98
US6118300ASep 12, 2000
Method for implementing large multiplexers with FPGA lookup tables
XILINX INC102 citations98
US6457164B1Sep 24, 2002
Hetergeneous method for determining module placement in FPGAs
XILINX INC103 citations97
US6292925B1Sep 18, 2001
Context-sensitive self implementing modules
XILINX INC90 citations97
US6216258B1Apr 10, 2001
FPGA modules parameterized by expressions
XILINX INC84 citations97
US6501296B2Dec 31, 2002
Logic/memory circuit having a plurality of operating modes
XILINX INC47 citations96
US6400180B2Jun 4, 2002
Configurable lookup table for programmable logic devices
XILINX INC71 citations96
US6260182B1Jul 10, 2001
Method for specifying routing in a logic module by direct module communication
XILINX INC70 citations96
US6243851B1Jun 5, 2001
Heterogeneous method for determining module placement in FPGAs
XILINX INC71 citations96
US6191610B1Feb 20, 2001
Method for implementing large multiplexers with FPGA lookup tables
XILINX INC46 citations96
US6184712B1Feb 6, 2001
FPGA configurable logic block with multi-purpose logic/memory circuit
XILINX INC60 citations96
US9218443B1Dec 22, 2015
Heterogeneous multiprocessor program compilation targeting programmable integrated circuits
XILINX INC59 citations95
US10866753B2Dec 15, 2020
Data processing engine arrangement in a device
XILINX INC15 citations94
US10802807B1Oct 13, 2020
Control and reconfiguration of data flow graphs on heterogeneous computing platform
XILINX INC25 citations93
US6847229B2Jan 25, 2005
Configurable logic element with expander structures
XILINX INC20 citations93
US6630841B2Oct 7, 2003
Configurable logic element with expander structures
XILINX INC14 citations93
US6505337B1Jan 7, 2003
Method for implementing large multiplexers with FPGA lookup tables
XILINX INC29 citations93
US7721090B1May 18, 2010
Event-driven simulation of IP using third party event-driven simulators
XILINX INC28 citations92
US6803786B1Oct 12, 2004
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
XILINX INC26 citations92
US6583645B1Jun 24, 2003
Field programmable optical arrays
XILINX INC38 citations92
US6353920B1Mar 5, 2002
Method for implementing wide gates and tristate buffers using FPGA carry logic
XILINX INC26 citations92
US6237129B1May 22, 2001
Method for constraining circuit element positions in structured layouts
XILINX INC34 citations92
US10747690B2Aug 18, 2020
Device with data processing engine array
XILINX INC19 citations85
US7111273B1Sep 19, 2006
Softpal implementation and mapping technology for FPGAs with dedicated resources
XILINX INC16 citations84
US6603332B2Aug 5, 2003
Configurable logic block for PLD with logic gate for combining output with another configurable logic block
XILINX INC17 citations84
US11281440B1Mar 22, 2022
Control and reconfiguration of data flow graphs on heterogeneous computing platform
XILINX INC5 citations83
US7310594B1Dec 18, 2007
Method and system for designing a multiprocessor
XILINX INC13 citations83
US7181718B1Feb 20, 2007
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
XILINX INC13 citations83
US7948269B1May 24, 2011
System and method for open drain/open collector structures in an integrated circuit
XILINX INC10 citations82
US7340585B1Mar 4, 2008
Method and system for fast linked processor in a system on a chip (SoC)
XILINX INC12 citations82
US6288569B1Sep 11, 2001
Memory array with hard and soft decoders
XILINX INC12 citations82
US7248073B2Jul 24, 2007
Configurable logic element with expander structures
XILINX INC7 citations74
US11573726B1Feb 7, 2023
Data processing engine arrangement in a device
XILINX INC1 citations73
US11204745B2Dec 21, 2021
Dataflow graph programming environment for a heterogenous processing system
XILINX INC4 citations72
US10990552B1Apr 27, 2021
Streaming interconnect architecture for data processing engine array
XILINX INC4 citations72
US10824434B1Nov 3, 2020
Dynamically structured single instruction, multiple data (SIMD) instructions
XILINX INC2 citations72
US10860766B1Dec 8, 2020
Compilation flow for a heterogeneous multi-core architecture
XILINX INC4 citations71
US9846660B2Dec 19, 2017
Heterogeneous multiprocessor platform targeting programmable integrated circuits
XILINX INC5 citations70
US7243330B1Jul 10, 2007
Method and apparatus for providing self-implementing hardware-software libraries
XILINX INC8 citations70
US7145360B2Dec 5, 2006
Configurable logic element with expander structures
XILINX INC3 citations63
US11972132B2Apr 30, 2024
Data processing engine arrangement in a device
XILINX INC0 citations62
US6946874B1Sep 20, 2005
Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
XILINX INC1 citations62
US11687327B2Jun 27, 2023
Control and reconfiguration of data flow graphs on heterogeneous computing platform
XILINX INC0 citations61
JAMES-ROXBY PHILIP B
2 patentsCARRILLO JORGE ERNESTO
1 patentPHILIPS CORP
1 patentShowing the top 50 of 54 patents by PatentIndex Score.