Inventor

HOTTA TAKASHI

JP81 patents

⚠️ This page may combine multiple inventors who share the name “HOTTA TAKASHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOTTA TAKASHI

HITACHI LTD

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Logic circuit module having power consumption control interface and a recording medium storing the module

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them

Information processor and information processing system utilizing clock signal

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Pipelined semiconductor devices suitable for ultra large scale integration

Semiconductor integrated circuit apparatus

Computer having a parallel operating capability

Semiconductor integrated circuit device

Dynamic logic circuit including bipolar transistors and field-effect transistors

Logic circuit module having power consumption control interface and a recording medium storing the module

Data processor having cache memory

Synchronization system and synchronization method of multisystem control apparatus

Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them

Information processor for performing processing without register conflicts

Information processor and information processing system utilizing clock signal

Data processor with variable types of cache memories

Floating-point addition/substraction processing apparatus and method thereof

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Current-driven signal interface implemented in semiconductor integrated circuit device

Semiconductor integrated circuit and method of designing the same

Template matching image processor utilizing sub image pixel sums and sum of squares thresholding

Method of controlling parallel processing at an instruction level and processor for realizing the method

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Data processor with variable types of cache memories and a controller for selecting a cache memory to be access

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Data processor having cache memory

Statistic calculating method using a template and corresponding sub-image to determine similarity based on sum of squares thresholding

Data processor having cache memory

Pipelined semiconductor devices suitable for ultra large scale integration

Data processor for the parallel processing of a plurality of instructions

Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them

Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory

Data processor providing plural decoders for effecting fast register selection

Instruction decode method and arrangement suitable for a decoder of microprocessors

Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Replicated controller and fault recovery method thereof

Microprocessor

Arithmetic unit capable of performing concurrent operations for high speed operation

HONDA MOTOR CO LTD

Planetary gear transmission

Lubricating oil supply structure in planetary gear mechanism

Parallel shaft transmission

Planetary gear mechanism

Lubrication structure for planetary gear assembly

MITSUBISHI ELECTRIC CORP

Apparatus for generating orthogonal sequences

RENESAS TECH CORP

Phase-locked loop circuit, information processing apparatus, and information processing system