Inventor

ARIMILLI RAVI KUMAR

US357 patents

⚠️ This page may combine multiple inventors who share the name “ARIMILLI RAVI KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMILLI RAVI KUMAR

IBM

Queued arbitration mechanism for data processing system

High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

Speculative execution of instructions and processes before completion of preceding barrier operations

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

Decentralized global coherency management in a multi-node computer system

Multi-level multiprocessor speculation mechanism

Multiprocessor speculation mechanism via a barrier speculation flag

Method and apparatus for servicing a processing system through a test port

Multiprocessor system bus protocol with group addresses, responses, and priorities

Programmable agent and method for managing prefetch queues

Method of cache management to dynamically update information-type dependent cache policies

Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response

Optimized cache allocation algorithm for multiple speculative requests

Method and system for bypassing cache levels when casting out from an upper level cache

Demand-based larx-reserve protocol for SMP system buses

Multiprocessor system supporting multiple outstanding TLBI operations per partition

Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction

Microprocessor reservation mechanism for a hashed address system

Selectable interface for interfacing integrated circuit modules

Multiprocessor speculation mechanism for efficiently managing multiple barrier operations

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

System and method for asynchronously overlapping storage barrier operations with old and new storage operations

ECC mechanism for set associative cache array

Integrated cache and directory structure for multi-level caches

Cache management mechanism to enable information-type dependent cache policies

Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data

Multiprocessor system bus protocol for O state memory-consistent data

Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

Cache coherency protocols with global and local posted operations

Multiprocessor system bus with a data-less castout mechanism

Eviction override for larx-reserved addresses

Cache coherency protocol for a data processing system including a multi-level memory hierarchy

High performance cache directory addressing scheme for variable cache sizes utilizing associativity

Forward progress on retried snoop hits by altering the coherency state of a local cache

Software-managed programmable unified/split caching mechanism for instructions and data

Cache coherency protocol with efficient write-through aliasing

Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states

Method and system for transferring data between buses having differing ordering policies

Dynamic updating of repair mask used for cache defect avoidance

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

Cache array defect functional bypassing using repair mask

Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations

Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization

Method and data processing system having dynamic profile-directed feedback at runtime

Cross partition sharing of state information

Method and system for supplier-based memory speculation in a memory subsystem of a data processing system

Data processing system and method with dynamic idle for tunable interface calibration

Data processing system providing hardware acceleration of input/output (I/O) communication

INTERNAT BUSINESS MACHNIES COR

Method, apparatus and system for allocating and accessing memory-mapped facilities within a data processing system