Inventor

DODSON JOHN STEVEN

US206 patents

Patents

50 patents

US6963967B1Nov 8, 2005

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

IBM71 citations98

US6880073B2Apr 12, 2005

Speculative execution of instructions and processes before completion of preceding barrier operations

IBM78 citations98

US6754782B2Jun 22, 2004

Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange

IBM59 citations96

US6625660B1Sep 23, 2003

Multiprocessor speculation mechanism for efficiently managing multiple barrier operations

IBM74 citations96

US6615322B2Sep 2, 2003

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

IBM70 citations96

US6609192B1Aug 19, 2003

System and method for asynchronously overlapping storage barrier operations with old and new storage operations

IBM70 citations96

US6480975B1Nov 12, 2002

ECC mechanism for set associative cache array

IBM53 citations96

US6345342B1Feb 5, 2002

Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

IBM75 citations96

US6330643B1Dec 11, 2001

Cache coherency protocols with global and local posted operations

IBM64 citations96

US6212605B1Apr 3, 2001

Eviction override for larx-reserved addresses

IBM67 citations96

US6192458B1Feb 20, 2001

High performance cache directory addressing scheme for variable cache sizes utilizing associativity

IBM78 citations96

US6192451B1Feb 20, 2001

Cache coherency protocol for a data processing system including a multi-level memory hierarchy

IBM67 citations96

US6138218AOct 24, 2000

Forward progress on retried snoop hits by altering the coherency state of a local cache

IBM57 citations96

US6058456AMay 2, 2000

Software-managed programmable unified/split caching mechanism for instructions and data

IBM70 citations96

US6021468AFeb 1, 2000

Cache coherency protocol with efficient write-through aliasing

IBM53 citations96

US6018791AJan 25, 2000

Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states

IBM78 citations96

US6006311ADec 21, 1999

Dynamic updating of repair mask used for cache defect avoidance

IBM74 citations96

US5974507AOct 26, 1999

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

IBM76 citations96

US5958068ASep 28, 1999

Cache array defect functional bypassing using repair mask

IBM58 citations96

US6970976B1Nov 29, 2005

Layered local cache with lower level cache optimizing allocation mechanism

IBM20 citations93

US6901485B2May 31, 2005

Memory directory management in a multi-node computer system

IBM46 citations93

US6801984B2Oct 5, 2004

Imprecise snooping based invalidation mechanism

IBM34 citations93

US6763434B2Jul 13, 2004

Data processing system and method for resolving a conflict between requests to modify a shared cache line

IBM22 citations93

US6763433B1Jul 13, 2004

High performance cache intervention mechanism for symmetric multiprocessor systems

IBM36 citations93

US6760809B2Jul 6, 2004

Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory

IBM23 citations93

US6760817B2Jul 6, 2004

Method and system for prefetching utilizing memory initiated prefetch write operations

IBM52 citations93

US6728873B1Apr 27, 2004

System and method for providing multiprocessor speculation within a speculative branch path

IBM24 citations93

US6725340B1Apr 20, 2004

Mechanism for folding storage barrier operations in a multiprocessor system

IBM31 citations93

US6721856B1Apr 13, 2004

Enhanced cache management mechanism via an intelligent system bus monitor

IBM33 citations93

US6711652B2Mar 23, 2004

Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data

IBM53 citations93

US6658538B2Dec 2, 2003

Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control

IBM52 citations93

US6633959B2Oct 14, 2003

Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data

IBM50 citations93

US6629210B1Sep 30, 2003

Intelligent cache management mechanism via processor access sequence analysis

IBM42 citations93

US6629209B1Sep 30, 2003

Cache coherency protocol permitting sharing of a locked data granule

IBM30 citations93

US6629212B1Sep 30, 2003

High speed lock acquisition mechanism with time parameterized cache coherency states

IBM38 citations93

US6625701B1Sep 23, 2003

Extended cache coherency protocol with a modified store instruction lock release indicator

IBM23 citations93

US6615321B2Sep 2, 2003

Mechanism for collapsing store misses in an SMP computer system

IBM26 citations93

US6606702B1Aug 12, 2003

Multiprocessor speculation mechanism with imprecise recycling of storage operations

IBM45 citations93

US6601144B1Jul 29, 2003

Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis

IBM53 citations93

US6587926B2Jul 1, 2003

Incremental tag build for hierarchical memory architecture

IBM19 citations93

US6587924B2Jul 1, 2003

Scarfing within a hierarchical memory architecture

IBM27 citations93

US6571322B2May 27, 2003

Multiprocessor computer system with sectored cache line mechanism for cache intervention

IBM45 citations93

US6553442B1Apr 22, 2003

Bus master for SMP execution of global operations utilizing a single token with implied release

IBM36 citations93

US6549989B1Apr 15, 2003

Extended cache coherency protocol with a “lock released” state

IBM35 citations93

Showing the top 50 of 206 patents by PatentIndex Score.

DODSON JOHN STEVEN

Patents

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

Speculative execution of instructions and processes before completion of preceding barrier operations

Decentralized global coherency management in a multi-node computer system

Multi-level multiprocessor speculation mechanism

Multiprocessor speculation mechanism via a barrier speculation flag

Programmable agent and method for managing prefetch queues

Optimized cache allocation algorithm for multiple speculative requests

Demand-based larx-reserve protocol for SMP system buses

Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange

Multiprocessor speculation mechanism for efficiently managing multiple barrier operations

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

System and method for asynchronously overlapping storage barrier operations with old and new storage operations

ECC mechanism for set associative cache array

Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

Cache coherency protocols with global and local posted operations

Eviction override for larx-reserved addresses

High performance cache directory addressing scheme for variable cache sizes utilizing associativity

Cache coherency protocol for a data processing system including a multi-level memory hierarchy

Forward progress on retried snoop hits by altering the coherency state of a local cache

Software-managed programmable unified/split caching mechanism for instructions and data

Cache coherency protocol with efficient write-through aliasing

Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states

Dynamic updating of repair mask used for cache defect avoidance

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

Cache array defect functional bypassing using repair mask

Layered local cache with lower level cache optimizing allocation mechanism

Memory directory management in a multi-node computer system

Imprecise snooping based invalidation mechanism

Data processing system and method for resolving a conflict between requests to modify a shared cache line

High performance cache intervention mechanism for symmetric multiprocessor systems

Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory

Method and system for prefetching utilizing memory initiated prefetch write operations

System and method for providing multiprocessor speculation within a speculative branch path

Mechanism for folding storage barrier operations in a multiprocessor system

Enhanced cache management mechanism via an intelligent system bus monitor

Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data

Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control

Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data

Intelligent cache management mechanism via processor access sequence analysis

Cache coherency protocol permitting sharing of a locked data granule

High speed lock acquisition mechanism with time parameterized cache coherency states

Extended cache coherency protocol with a modified store instruction lock release indicator

Mechanism for collapsing store misses in an SMP computer system

Multiprocessor speculation mechanism with imprecise recycling of storage operations

Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis

Incremental tag build for hierarchical memory architecture

Scarfing within a hierarchical memory architecture

Multiprocessor computer system with sectored cache line mechanism for cache intervention

Bus master for SMP execution of global operations utilizing a single token with implied release

Extended cache coherency protocol with a “lock released” state