Inventor

LEWIS JERRY DON

US141 patents

Patents

50 patents

US6848003B1Jan 25, 2005

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

IBM87 citations98

US6591321B1Jul 8, 2003

Multiprocessor system bus protocol with group addresses, responses, and priorities

IBM89 citations98

US5895495AApr 20, 1999

High performance cache directory addressing scheme for variable cache sizes utilizing associativity

IBM78 citations96

US6192451B1Feb 20, 2001

Cache coherency protocol for a data processing system including a multi-level memory hierarchy

IBM67 citations96

US6138218AOct 24, 2000

Forward progress on retried snoop hits by altering the coherency state of a local cache

IBM57 citations96

US6058456AMay 2, 2000

Software-managed programmable unified/split caching mechanism for instructions and data

IBM70 citations96

US6021468AFeb 1, 2000

Cache coherency protocol with efficient write-through aliasing

IBM53 citations96

US6018791AJan 25, 2000

Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states

IBM78 citations96

US6006311ADec 21, 1999

Dynamic updating of repair mask used for cache defect avoidance

IBM74 citations96

US5974507AOct 26, 1999

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

IBM76 citations96

US5958068ASep 28, 1999

Cache array defect functional bypassing using repair mask

IBM58 citations96

US6910062B2Jun 21, 2005

Method and apparatus for transmitting packets within a symmetric multiprocessor system

IBM19 citations93

US6801984B2Oct 5, 2004

Imprecise snooping based invalidation mechanism

IBM34 citations93

US6591307B1Jul 8, 2003

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

IBM25 citations93

US6587926B2Jul 1, 2003

Incremental tag build for hierarchical memory architecture

IBM19 citations93

US6587924B2Jul 1, 2003

Scarfing within a hierarchical memory architecture

IBM27 citations93

US6553442B1Apr 22, 2003

Bus master for SMP execution of global operations utilizing a single token with implied release

IBM36 citations93

US6516368B1Feb 4, 2003

Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release

IBM27 citations93

US6507880B1Jan 14, 2003

Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens

IBM25 citations93

US6502171B1Dec 31, 2002

Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data

IBM48 citations93

US6502168B1Dec 31, 2002

Cache having virtual cache controller queues

IBM22 citations93

US6477613B1Nov 5, 2002

Cache index based system address bus

IBM25 citations93

US6460101B1Oct 1, 2002

Token manager for execution of global operations utilizing multiple tokens

IBM20 citations93

US6427204B1Jul 30, 2002

Method for just in-time delivery of instructions in a data processing system

IBM22 citations93

US6418514B1Jul 9, 2002

Removal of posted operations from cache operations queue

IBM27 citations93

US6415358B1Jul 2, 2002

Cache coherency protocol having an imprecise hovering (H) state for instructions and data

IBM25 citations93

US6374330B1Apr 16, 2002

Cache-coherency protocol with upstream undefined state

IBM19 citations93

US6353875B1Mar 5, 2002

Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions

IBM47 citations93

US6347363B1Feb 12, 2002

Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches

IBM22 citations93

US6345340B1Feb 5, 2002

Cache coherency protocol with ambiguous state for posted operations

IBM19 citations93

US6343344B1Jan 29, 2002

System bus directory snooping mechanism for read/castout (RCO) address transaction

IBM43 citations93

US6343347B1Jan 29, 2002

Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction

IBM49 citations93

US6334172B1Dec 25, 2001

Cache coherency protocol with tagged state for modified values

IBM35 citations93

US6292872B1Sep 18, 2001

Cache coherency protocol having hovering (H) and recent (R) states

IBM24 citations93

US6275909B1Aug 14, 2001

Multiprocessor system bus with system controller explicitly updating snooper cache state information

IBM48 citations93

US6263407B1Jul 17, 2001

Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode

IBM20 citations93

US6195729B1Feb 27, 2001

Deallocation with cache update protocol (L2 evictions)

IBM43 citations93

US6185658B1Feb 6, 2001

Cache with enhanced victim selection using the coherency states of cache lines

IBM37 citations93

US6182201B1Jan 30, 2001

Demand-based issuance of cache operations to a system bus

IBM36 citations93

US6175930B1Jan 16, 2001

Demand based sync bus operation

IBM39 citations93

US6161189ADec 12, 2000

Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies

IBM21 citations93

US6157980ADec 5, 2000

Cache directory addressing scheme for variable cache sizes

IBM37 citations93

US6145059ANov 7, 2000

Cache coherency protocols with posted operations and tagged coherency states

IBM38 citations93

US6141733AOct 31, 2000

Cache coherency protocol with independent implementation of optimized cache operations

IBM39 citations93

US6128707AOct 3, 2000

Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles

IBM21 citations93

US6085288AJul 4, 2000

Dual cache directories with respective queue independently executing its content and allowing staggered write operations

IBM29 citations93

Showing the top 50 of 141 patents by PatentIndex Score.

LEWIS JERRY DON

Patents

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

Multiprocessor system bus protocol with group addresses, responses, and priorities

Demand-based larx-reserve protocol for SMP system buses

ECC mechanism for set associative cache array

Cache coherency protocols with global and local posted operations

Eviction override for larx-reserved addresses

High performance cache directory addressing scheme for variable cache sizes utilizing associativity

Cache coherency protocol for a data processing system including a multi-level memory hierarchy

Forward progress on retried snoop hits by altering the coherency state of a local cache

Software-managed programmable unified/split caching mechanism for instructions and data

Cache coherency protocol with efficient write-through aliasing

Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states

Dynamic updating of repair mask used for cache defect avoidance

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

Cache array defect functional bypassing using repair mask

Method and apparatus for transmitting packets within a symmetric multiprocessor system

Imprecise snooping based invalidation mechanism

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

Incremental tag build for hierarchical memory architecture

Scarfing within a hierarchical memory architecture

Bus master for SMP execution of global operations utilizing a single token with implied release

Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release

Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens

Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data

Cache having virtual cache controller queues

Cache index based system address bus

Token manager for execution of global operations utilizing multiple tokens

Method for just in-time delivery of instructions in a data processing system

Removal of posted operations from cache operations queue

Cache coherency protocol having an imprecise hovering (H) state for instructions and data

Cache-coherency protocol with upstream undefined state

Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions

Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches

Cache coherency protocol with ambiguous state for posted operations

System bus directory snooping mechanism for read/castout (RCO) address transaction

Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction

Cache coherency protocol with tagged state for modified values

Cache coherency protocol having hovering (H) and recent (R) states

Multiprocessor system bus with system controller explicitly updating snooper cache state information

Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode

Deallocation with cache update protocol (L2 evictions)

Cache with enhanced victim selection using the coherency states of cache lines

Demand-based issuance of cache operations to a system bus

Demand based sync bus operation

Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies

Cache directory addressing scheme for variable cache sizes

Cache coherency protocols with posted operations and tagged coherency states

Cache coherency protocol with independent implementation of optimized cache operations

Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles

Dual cache directories with respective queue independently executing its content and allowing staggered write operations