Inventor

MITSUMOTO KINYA

JP26 patents

⚠️ This page may combine multiple inventors who share the name “MITSUMOTO KINYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MITSUMOTO KINYA

HITACHI LTD

Semiconductor device

Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit

Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device

Synchronous memory with pipelined write operation

Semiconductor memory device and sense circuit

Reference current generating circuit for generating a constant current

Semiconductor memory with multiple sets &amp; redundant cells

Memory device with improved common data line bias arrangement

Write circuit for use in semiconductor storage device

High-speed semiconductor memory device and data processing system using the same

Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels

Memory device with improved common data line bias arrangement

Semiconductor memory device

Semiconductor memory device with matched equivalent series resistances to the complementary data lines

Semiconductor integrated circuit device with two variable delay lines in writing circuit control

Semiconductor memory device

Semiconductor memory device

RENESAS TECH CORP

Synchronization circuit and synchronization method

Synchronization circuit and synchronization method

Semiconductor memory device having a double data rate (DDR) mode and utilizing a plurality of comparison circuits to prevent errors due to a late write function

Semiconductor device and method of manufacturing a semiconductor device

Semiconductor memory device

Semiconductor device

Semiconductor device

HITACHI ULSI SYS CO LTD

Semiconductor memory device

Semiconductor memory device

Semiconductor memory with multiple sets & redundant cells