P

Inventor

HINEMAN MAX F

US35 patents
⚠️ This page may combine multiple inventors who share the name “HINEMAN MAX F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MICRON TECHNOLOGY INC

26 patents
US6372657B1Apr 16, 2002

Method for selective etching of oxides

MICRON TECHNOLOGY INC188 citations99
US6358756B1Mar 19, 2002

Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme

MICRON TECHNOLOGY INC163 citations98
US6350679B1Feb 26, 2002

Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry

MICRON TECHNOLOGY INC336 citations98
US6521931B2Feb 18, 2003

Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme

MICRON TECHNOLOGY INC47 citations96
US6486108B1Nov 26, 2002

Cleaning composition useful in semiconductor integrated circuit fabrication

MICRON TECHNOLOGY INC41 citations96
US6613681B1Sep 2, 2003

Method of removing etch residues

MICRON TECHNOLOGY INC25 citations90
US7135444B2Nov 14, 2006

Cleaning composition useful in semiconductor integrated circuit fabrication

MICRON TECHNOLOGY INC6 citations74
US6797628B2Sep 28, 2004

Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry

MICRON TECHNOLOGY INC6 citations74
US6638843B1Oct 28, 2003

Method for forming a silicide gate stack for use in a self-aligned contact etch

MICRON TECHNOLOGY INC9 citations74
US6547979B1Apr 15, 2003

Methods of enhancing selectivity of etching silicon dioxide relative to one or more organic substances; and plasma reaction chambers

MICRON TECHNOLOGY INC4 citations74
US6844255B2Jan 18, 2005

Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry

MICRON TECHNOLOGY INC7 citations73
US7344975B2Mar 18, 2008

Method to reduce charge buildup during high aspect ratio contact etch

MICRON TECHNOLOGY INC5 citations72
US7319071B2Jan 15, 2008

Methods for forming a metallic damascene structure

MICRON TECHNOLOGY INC5 citations63
US7131391B2Nov 7, 2006

Plasma reaction chamber liner comprising ruthenium

MICRON TECHNOLOGY INC2 citations63
US7087561B2Aug 8, 2006

Cleaning composition useful in semiconductor integrated circuit fabrication

MICRON TECHNOLOGY INC2 citations63
US7067466B2Jun 27, 2006

Cleaning composition useful in semiconductor integrated circuit fabrication

MICRON TECHNOLOGY INC1 citations63
US7985692B2Jul 26, 2011

Method to reduce charge buildup during high aspect ratio contact etch

MICRON TECHNOLOGY INC2 citations61
US7022612B2Apr 4, 2006

Method of removing etch residues

MICRON TECHNOLOGY INC2 citations60
US7615164B2Nov 10, 2009

Plasma etching methods and contact opening forming methods

MICRON TECHNOLOGY INC0 citations52
US7293526B2Nov 13, 2007

Plasma reaction chamber liner consisting essentially of osmium

MICRON TECHNOLOGY INC0 citations52
US7255803B2Aug 14, 2007

Method of forming contact openings

MICRON TECHNOLOGY INC0 citations52
US7118683B2Oct 10, 2006

Methods of etching silicon-oxide-containing compositions

MICRON TECHNOLOGY INC0 citations52
US7067465B2Jun 27, 2006

Cleaning composition useful in semiconductor integrated circuit fabricating

MICRON TECHNOLOGY INC0 citations52
US7067429B2Jun 27, 2006

Processing method of forming MRAM circuitry

MICRON TECHNOLOGY INC0 citations52
US6953531B2Oct 11, 2005

Methods of etching silicon-oxide-containing materials

MICRON TECHNOLOGY INC0 citations52
US6831047B2Dec 14, 2004

Cleaning composition useful in semiconductor integrated circuit fabrication

MICRON TECHNOLOGY INC0 citations52

INTEL CORP

6 patents

INNOVATIVE LASERS CORP

1 patent

SANDHU GURTEJ S

1 patent

KOVAL RANDY J

1 patent