Inventor

WANG LAUNG-TERNG L-T

US19 patents

⚠️ This page may combine multiple inventors who share the name “WANG LAUNG-TERNG L-T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG LAUNG-TERNG L-T

SYNTEST TECHNOLOGIES INC

Method and apparatus for broadcasting test patterns in a scan based integrated circuit

Mask network design for scan-based integrated circuits

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for scan-based integrated circuits

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Method and apparatus for pipelined scan compression

X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Method and apparatus for multi-level scan compression

Computer-aided design system to automate scan synthesis at register-transfer level

Compacting test responses using X-driven compactor

Mask network design for scan-based integrated circuits

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

Method and apparatus for pipelined scan compression

Method for performing ATPG and fault simulation in a scan-based integrated circuit

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Multiple-capture DFT system for scan-based integrated circuits

IEEE Std. 1149.4 compatible analog BIST methodology

WANG LAUNG-TERNG L-T

Computer-aided design system to automate scan synthesis at register-transfer level