Inventor

WEN XIAOQING

US44 patents

⚠️ This page may combine multiple inventors who share the name “WEN XIAOQING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEN XIAOQING

SYNTEST TECHNOLOGIES INC

Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Mask network design for scan-based integrated circuits

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Computer-aided design system to automate scan synthesis at register-transfer level

Multiple-capture DFT system for scan-based integrated circuits

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Computer-aided design system to automate scan synthesis at register-transfer level

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

Computer-aided design system to automate scan synthesis at register-transfer level

Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits

Computer-aided design system to automate scan synthesis at register-transfer level

Compacting test responses using X-driven compactor

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Mask network design for scan-based integrated circuits

Multiple-capture DFT system for scan-based integrated circuits

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for scan-based integrated circuits

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

JAPAN SCIENCE & TECH AGENCY

Generating device, generating method, program and recording medium

Generating device, generating method, program and recording medium

Conversion device, conversion method, program, and recording medium

Diagnostic device, diagnostic method, program, and recording medium

KYUSHU INST TECHNOLOGY

Test vector generating method and test vector generating program of semiconductor logic circuit device

Method and apparatus of fault diagnosis for integrated logic circuits

Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

MIYASE KOHEI

Don&#39;t-care-bit identification method and don&#39;t-care-bit identification program

Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium

Generating device, generating method, and program

SYNTEST TECH INC

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

WANG LAUNG-TERNG

Computer-aided design system to automate scan synthesis at register-transfer level

TENCENT TECH SHENZHEN CO LTD

Virtual object control method and apparatus, terminal, and storage medium

WANG LAUNG-TERNG L-T

Computer-aided design system to automate scan synthesis at register-transfer level

WEN XIAOQING

Test method and test program of semiconductor logic circuit device

Don't-care-bit identification method and don't-care-bit identification program