Inventor
SHEU BORYAU JACK
US11 patents
Patents
11 patentsUS7412637B2Aug 12, 2008
Method and apparatus for broadcasting test patterns in a scan based integrated circuit
SYNTEST TECHNOLOGIES INC62 citations97
US7032148B2Apr 18, 2006
Mask network design for scan-based integrated circuits
SYNTEST TECHNOLOGIES INC84 citations96
US7945833B1May 17, 2011
Method and apparatus for pipelined scan compression
SYNTEST TECHNOLOGIES INC29 citations92
US7231570B2Jun 12, 2007
Method and apparatus for multi-level scan compression
SYNTEST TECHNOLOGIES INC21 citations92
US7512851B2Mar 31, 2009
Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
SYNTEST TECHNOLOGIES INC39 citations91
US7124342B2Oct 17, 2006
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
SYNTEST TECHNOLOGIES INC31 citations91
US7779322B1Aug 17, 2010
Compacting test responses using X-driven compactor
SYNTEST TECHNOLOGIES INC12 citations84
US7735049B2Jun 8, 2010
Mask network design for scan-based integrated circuits
SYNTEST TECHNOLOGIES INC8 citations84
US7721172B2May 18, 2010
Method and apparatus for broadcasting test patterns in a scan-based integrated circuit
SYNTEST TECHNOLOGIES INC11 citations83
US7590905B2Sep 15, 2009
Method and apparatus for pipelined scan compression
SYNTEST TECHNOLOGIES INC13 citations83
US7210082B1Apr 24, 2007
Method for performing ATPG and fault simulation in a scan-based integrated circuit
SYNTEST TECHNOLOGIES INC16 citations83