Inventor

LU JIONG-PING

US66 patents

⚠️ This page may combine multiple inventors who share the name “LU JIONG-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU JIONG-PING

TEXAS INSTRUMENTS INC

Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density

Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures

Integrated circuit dielectric and method

Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing

Integrated circuit dielectric and method

Reliable interconnects with low via/contact resistance

CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes

Method of forming diffusion barriers for copper metallization in integrated cirucits

Copper bond pad process

TiN+Al films and processes

Method for forming a conductive copper structure

Low resistivity poly-silicon gate produced by selective metal growth

Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Method for fabricating dual work function metal gates

Semiconductor device having a fully silicided gate electrode and method of manufacture therefor

Si-rich surface layer capped diffusion barriers

In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability

Method for manufacturing a semiconductor device containing metal silicide regions

Pre-ECD wet surface modification to improve wettability and reduced void defect

Method for manufacturing a semiconductor device having silicided regions

Integration scheme for using silicided dual work function metal gates

Integrated circuit dielectric and method

Barrier/liner with a SiNx-enriched surface layer on MOCVD prepared films

Silicide method for CMOS integrated circuits

Copper surface passivation during semiconductor manufacturing

Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices

Tungsten-nitride for contact barrier application

Methods for providing improved layer adhesion in a semiconductor device

Methods for chemical vapor deposition of tungsten on silicon or dielectric

Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device

Process for defect reduction in electrochemical plating

Plating-rinse-plating process for fabricating copper interconnects

NiSi metal gate stacks using a boron-trap

Process for depositing thin films containing titanium and nitrogen

FUSI integration method using SOG as a sacrificial planarization layer

System for reducing silicon-consumption through selective deposition

Silicide formation using a low temperature anneal process

Semiconductor devices and methods of manufacturing such semiconductor devices

Process method to facilitate silicidation

Integrated circuit metal silicide method

Nickel silicide—silicon nitride adhesion through surface passivation

Use of a sacrificial layer to facilitate metallization for small features

Process for isolating an exposed conducting surface

Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process

MICRON TECHNOLOGY INC

High-k dielectric materials and processes for manufacturing them

High-k dielectric materials and processes for manufacturing them

High-K dielectric materials and processes for manufacturing them

High-k dielectric materials and processes for manufacturing them

TEXAS INSTURMENTS INC

System for preventing excess silicon consumption in ultra shallow junctions

WEIJTMANS JOHAN

Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe