Inventor
GOSWAMI DHIRAJ
US24 patents
⚠️ This page may combine multiple inventors who share the name “GOSWAMI DHIRAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
11 patentsUS6311317B1Oct 30, 2001
Pre-synthesis test point insertion
SYNOPSYS INC91 citations97
US9202005B2Dec 1, 2015
Development and debug environment in a constrained random verification
SYNOPSYS INC13 citations78
US9958917B1May 1, 2018
Generalized resettable memory
SYNOPSYS INC3 citations72
US10762262B1Sep 1, 2020
Multi-dimensional constraint solver using modified relaxation process
SYNOPSYS INC5 citations71
US11853668B1Dec 26, 2023
FPGA implementation interleaved with FPGA overlay architectures for emulation
SYNOPSYS INC1 citations62
US8370273B2Feb 5, 2013
Method and apparatus for constructing a canonical representation
SYNOPSYS INC2 citations62
US10325046B2Jun 18, 2019
Formal method for clock tree analysis and optimization
SYNOPSYS INC1 citations56
US8904320B2Dec 2, 2014
Solving multiplication constraints by factorization
SYNOPSYS INC3 citations54
US11468218B2Oct 11, 2022
Information theoretic subgraph caching
SYNOPSYS INC0 citations51
US10372856B2Aug 6, 2019
Optimizing constraint solving by rewriting at least one bit-slice constraint
SYNOPSYS INC0 citations49
US9098665B2Aug 4, 2015
Prioritized soft constraint solving
SYNOPSYS INC0 citations49
GOSWAMI DHIRAJ
4 patentsUS7555689B2Jun 30, 2009
Generating responses to patterns stimulating an electronic circuit with timing exception paths
GOSWAMI DHIRAJ27 citations91
US8099690B2Jan 17, 2012
Adaptive state-to-symbolic transformation in a canonical representation
GOSWAMI DHIRAJ13 citations81
US9720792B2Aug 1, 2017
Information theoretic caching for dynamic problem generation in constraint solving
GOSWAMI DHIRAJ3 citations71
US9069699B2Jun 30, 2015
Identifying inconsistent constraints
GOSWAMI DHIRAJ0 citations50
CADENCE DESIGN SYSTEMS INC
4 patentsUS11676068B1Jun 13, 2023
Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis
CADENCE DESIGN SYSTEMS INC4 citations73
US11687831B1Jun 27, 2023
Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference
CADENCE DESIGN SYSTEMS INC2 citations71
US11615320B1Mar 28, 2023
Method, product, and apparatus for variable precision weight management for neural networks
CADENCE DESIGN SYSTEMS INC3 citations71
US12536364B1Jan 27, 2026
Fanout-based combinational loop emulation
CADENCE DESIGN SYSTEMS INC0 citations48