Inventor
JARRAR ANIS M
US19 patents
⚠️ This page may combine multiple inventors who share the name “JARRAR ANIS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
8 patentsUS7681106B2Mar 16, 2010
Error correction device and methods thereof
FREESCALE SEMICONDUCTOR INC106 citations94
US8710906B1Apr 29, 2014
Fine grain voltage scaling of back biasing
FREESCALE SEMICONDUCTOR INC8 citations82
US9285813B2Mar 15, 2016
Supply voltage regulation with temperature scaling
FREESCALE SEMICONDUCTOR INC3 citations72
US9806019B2Oct 31, 2017
Integrated circuit with power saving feature
FREESCALE SEMICONDUCTOR INC2 citations68
US7716511B2May 11, 2010
Dynamic timing adjustment in a circuit device
FREESCALE SEMICONDUCTOR INC5 citations62
US7418675B2Aug 26, 2008
System and method for reducing the power consumption of clock systems
FREESCALE SEMICONDUCTOR INC5 citations59
US9264040B2Feb 16, 2016
Low leakage CMOS cell with low voltage swing
FREESCALE SEMICONDUCTOR INC0 citations37
US10094873B2Oct 9, 2018
High capacity I/O (input/output) cells
FREESCALE SEMICONDUCTOR INC0 citations36
JARRAR ANIS M
7 patentsUS8339177B2Dec 25, 2012
Multiple function power domain level shifter
JARRAR ANIS M27 citations86
US9264021B1Feb 16, 2016
Multi-bit flip-flop with enhanced fault detection
JARRAR ANIS M8 citations81
US8624627B1Jan 7, 2014
Method and device for low power control
JARRAR ANIS M17 citations81
US9088280B2Jul 21, 2015
Body bias control circuit
JARRAR ANIS M4 citations71
US9425775B2Aug 23, 2016
Low swing flip-flop with reduced leakage slave latch
JARRAR ANIS M3 citations69
US8604853B1Dec 10, 2013
State retention supply voltage distribution using clock network shielding
JARRAR ANIS M3 citations62
US9438242B2Sep 6, 2016
Systems and methods for reducing power consumption in semiconductor devices
JARRAR ANIS M1 citations49