Inventor

DOBLAR DREW G

US51 patents

⚠️ This page may combine multiple inventors who share the name “DOBLAR DREW G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOBLAR DREW G

SUN MICROSYSTEMS INC

Memory subsystem including memory modules having multiple banks

Computer system employing redundant cooling fans

Computer system including multiple clock sources and failover switching

Digital data transmission via multi-valued logic signals generated using multiple drive states each causing a different amount of current to flow through a termination resistor

System and method for providing master and slave phase-aligned clocks

Memory module having balanced data I/O contacts pads

Memory module with equal driver loading

High-performance memory module

Breakout board using blind vias to eliminate stubs

Computer system employing redundant power distribution

Phase locked loop and method that provide fail-over redundant clocking

Simultaneous bidirectional data transmission system and method

Encoded clocks to distribute multiple clock signals to multiple devices in a computer system

Phase locked loop and method that provide fail-over redundant clocking

System memory board subsystem using DRAM with stacked dedicated high speed point to point links

Source synchronous bus repeater

Circuit board orientation in a computer system

Computer system providing low skew clock signals to a synchronous memory unit

Computer system providing low skew clock signals to a synchronous memory unit

Electrical connector for conveying signals between two circuit boards

Reliable startup and steady-state of estimation based CDR and DFE

System memory board subsystem using DRAM with integrated high speed point to point links

Reliability clock domain crossing

Centerplaneless computer system

Optical transmitter for transmitting a plurality of output signals

Clock divider for analysis of all clock edges

Communication controllers and methods therefor

Computer system including network slices that map to field replaceable units

Compensation circuit for low phase offset for phase-locked loops

Encoded clocks to distribute multiple clock signals to multiple devices in a computer system

ORACLE AMERICA INC

Eye diagram determination during system operation

Voltage regulator attach for high current chip applications

Printed circuit board with optimized mounting holes and alignment pins

Memory system including independent isolated power for each memory module

Mechanism for constructing an oversampled waveform for a set of signals received by a receiver

HUANG DAWEI

Analog baud rate clock and data recovery

Integrated equalization and CDR adaptation engine with single error monitor circuit

System and method of adapting precursor tap coefficient

Asymmetric decision feedback equalization slicing in high speed transceivers

Real-time optimization of TX FIR filter for high-speed data communication

DOBLAR DREW G

Serial link voltage margin determination in mission mode

Low jitter and high bandwidth clock data recovery

Method and system for reducing duty cycle distortion amplification in forwarded clocks

Method for system energy use management of current shared power supplies

BUSHUE MICHAEL

Autonomous control in current share power supplies

Reducing latency when activating a power supply unit

SANMINA CORP

Delay circuitry to hold up power to a mass storage device and method therefor

YOON DONG J

Power and area efficient SerDes transmitter

SONG DEQIANG

Mechanism for constructing an oversampled waveform for a set of signals received by a receiver

LEE JUYOUNG

Extraction of component models from PCB channel scattering parameter data by stochastic optimization