P

Inventor

JAEGER DANIEL J

US12 patents
⚠️ This page may combine multiple inventors who share the name “JAEGER DANIEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

5 patents
US8053301B2Nov 8, 2011

CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess

IBM27 citations91
US9299795B2Mar 29, 2016

Partial sacrificial dummy gate with CMOS device with high-k metal gate

IBM3 citations73
US9041076B2May 26, 2015

Partial sacrificial dummy gate with CMOS device with high-k metal gate

IBM4 citations73
US9853116B2Dec 26, 2017

Partial sacrificial dummy gate with CMOS device with high-k metal gate

IBM0 citations52
US8629028B2Jan 14, 2014

Metal oxide semiconductor field effect transistor (MOSFET) gate termination

IBM1 citations51

WALLNER THOMAS A

2 patents
US8129234B2Mar 6, 2012

Method of forming bipolar transistor integrated with metal gate CMOS devices

WALLNER THOMAS A14 citations80
US8569840B2Oct 29, 2013

Bipolar transistor integrated with metal gate CMOS devices

WALLNER THOMAS A0 citations48

VEGA REINALDO A

1 patent
US9035430B2May 19, 2015

Semiconductor fin on local oxide

VEGA REINALDO A9 citations82

GLOBALFOUNDRIES US INC

1 patent
US11056398B2Jul 6, 2021

Forming interconnect without gate cut isolation blocking opening formation

GLOBALFOUNDRIES US INC0 citations56

BAIOCCO CHRISTOPHER V

1 patent
US8704332B2Apr 22, 2014

Metal oxide semiconductor field effect transistor (MOSFET) gate termination

BAIOCCO CHRISTOPHER V0 citations44

GLOBALFOUNDRIES INC

1 patent
US10714376B2Jul 14, 2020

Method of forming semiconductor material in trenches having different widths, and related structures

GLOBALFOUNDRIES INC0 citations41

AQUILINO MICHAEL V

1 patent
US8859388B2Oct 14, 2014

Sealed shallow trench isolation region

AQUILINO MICHAEL V0 citations39