Inventor

KRISHNAN RISHIKESH

US46 patents

⚠️ This page may combine multiple inventors who share the name “KRISHNAN RISHIKESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRISHNAN RISHIKESH

IBM

Single crystal source-drain merged by polycrystalline material

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Hydroxyl group termination for nucleation of a dielectric metallic oxide

finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

Stacked FETS with non-shared work function metals

Replacement gate with reduced gate leakage current

Buried power rails located in a base layer including first, second, and third etch stop layers

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

Gate oxide for nanosheet transistor devices

Gate oxide for nanosheet transistor devices

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Trench metal insulator metal capacitor with oxygen gettering layer

Hydroxyl group termination for nucleation of a dielectric metallic oxide

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

Trench metal-insulator-metal capacitor with oxygen gettering layer

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

Die level chemical mechanical polishing

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

Non-volatile memory structure employing high-k gate dielectric and metal gate

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

GLOBALFOUNDRIES INC

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Epitaxial growth of material on source/drain regions of FinFET structure

Microwave annealing of flowable oxides with trap layers

Fin structures

Device with highly active acceptor doping and method of production thereof

Wafer stress control with backside patterning

KRISHNAN RISHIKESH

Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor

Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials

Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials

Capacitors having dielectric regions that include multiple metal oxide-comprising materials

Capacitors having dielectric regions that include multiple metal oxide-comprising materials

Electrical components for microelectronic devices and methods of forming the same

MICRON TECHNOLOGY INC

Electrical components for microelectronic devices and methods of forming the same

Methods of making crystalline tantalum pentoxide

Electrical components for microelectronic devices

Electrical components for microelectronic devices and methods of forming the same

BHAT VISHWANATH

Methods of making crystalline tantalum pentoxide

Methods of making crystalline tantalum pentoxide

ANDO TAKASHI

Replacement gate with reduced gate leakage current

BREIL NICOLAS

Non-volatile memory structure employing high-k gate dielectric and metal gate

CHUDZIK MICHAEL P

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

FANG SUNFEI

Shallow trench isolation for device including deep trench capacitors

SHEPARD JR JOSEPH F

Insulating layers on different semiconductor materials