Inventor

LIM SU WEI

MY49 patents

⚠️ This page may combine multiple inventors who share the name “LIM SU WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIM SU WEI

INTEL CORP

Architected protocol for changing link operating mode

Architected protocol for changing link operating mode

Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests

Techniques for inter-component communication based on a state of a chip select pin

Inter-component communication including posted and non-posted transactions

Inter-component communication including slave component initiated transaction

Multichip package link

System and method for power management

Link equalization mechanism

Systems, apparatuses, and methods for synchronizing port entry into a low power status

Hardware mechanisms for link encryption

Dual bus standard switching bus controller

Method, apparatus and system for single-ended communication of transaction layer packets

Virtualized link states of multiple protocol layer package interconnects

Virtualized link states of multiple protocol layer package interconnects

Virtualized link states of multiple protocol layer package interconnects

Techniques enabling low power states for a communications port

Device, method and system for operation of a low power PHY with a PCIe protocol stack

Integrated universal serial bus (USB) type-C switching

Architected protocol for changing link operating mode

Inter-component communication using an interface including master and slave communication

PCI to PCI express protocol conversion

System, apparatus and method for synchronizing multiple virtual link states over a package interconnect

System, apparatus and method for synchronizing multiple virtual link states over a package interconnect

Reduced pin count interface

Method, apparatus, and system for power management on a CPU die via clock request messaging protocol

Low overheard high throughput solution for point-to-point link

Techniques for inter-component communication based on a state of a chip select pin

Inter-component communication including posted and non-posted transactions

Inter-component communication including posted and non-posted transactions

Dual bus standard switching bus controller

System and method for power management

Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle

Reduced pin count interface

Reduced pin count interface

Systems and methods for communicating encrypted time-related data

WAGH MAHESH

Systems, apparatuses, and methods for synchronizing port entry into a low power state

Systems, apparatuses, and methods for handling timeouts

MICRON TECHNOLOGY INC

Memory compression with improved lookup table scheme

Memory failure prediction and mitigation

GUOK NGEK LEONG

Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone

Method and apparatus for agent interfacing with pipeline backbone to locally handle transactions while obeying ordering rule

HUNSAKER MIKAL C

Apparatuses for inter-component communication including slave component initiated transaction

SONG TING LOK

Dual bus standard switching bus controller

TEH CHEE HAK

Controllable transaction synchronization for merging peripheral devices

SK HYNIX NAND PRODUCT SOLUTIONS CORP

Root complex integrated endpoint emulation of a discreet PCIE endpoint

LIM SU WEI

Method, apparatus, and system to handle transactions received after a configuration change request

LIM MING YI

Method and apparatus for clock frequency ratio independent error logging

TEOH POH THIAM

Power mangement techniques for an input/output (I/O) subsystem