Inventor
CHECK MARK A
US25 patents
⚠️ This page may combine multiple inventors who share the name “CHECK MARK A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS7617410B2Nov 10, 2009
Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock
IBM26 citations92
US6865645B1Mar 8, 2005
Program store compare handling between instruction and operand caches
IBM27 citations92
US7167968B2Jan 23, 2007
Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data
IBM20 citations90
US7739545B2Jun 15, 2010
System and method to support use of bus spare wires in connection modules
IBM8 citations82
US7089408B2Aug 8, 2006
Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution
IBM14 citations81
US10102165B2Oct 16, 2018
Arbitration in an SRIOV environment
IBM3 citations73
US6671794B1Dec 30, 2003
Address generation interlock detection
IBM11 citations73
US5625808AApr 29, 1997
Read only store as part of cache store for storing frequently used millicode instructions
IBM11 citations69
US7103754B2Sep 5, 2006
Computer instructions for having extended signed displacement fields for finding instruction operands
IBM2 citations63
US7035986B2Apr 25, 2006
System and method for simultaneous access of the same line in cache storage
IBM3 citations63
US6990556B2Jan 24, 2006
System and method for simultaneous access of the same doubleword in cache storage
IBM2 citations63
US6745313B2Jun 1, 2004
Absolute address bits kept in branch history table
IBM4 citations63
US7725894B2May 25, 2010
Enhanced un-privileged computer instruction to store a facility list
IBM5 citations62
US10255450B2Apr 9, 2019
Customer load of field programmable gate arrays
IBM0 citations52
US10108569B2Oct 23, 2018
Arbitration in an SRIOV environment
IBM0 citations52
US9875367B2Jan 23, 2018
Customer load of field programmable gate arrays
IBM0 citations52
US9703973B2Jul 11, 2017
Customer load of field programmable gate arrays
IBM1 citations52
US6973552B2Dec 6, 2005
System and method to handle page validation with out-of-order fetch
IBM0 citations52
US6751708B2Jun 15, 2004
Method for ensuring that a line is present in an instruction cache
IBM1 citations52
US7886089B2Feb 8, 2011
Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance
IBM0 citations51