Inventor

PRASKY BRIAN R

US147 patents

⚠️ This page may combine multiple inventors who share the name “PRASKY BRIAN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRASKY BRIAN R

IBM

Auxiliary branch prediction with usefulness tracking

Branch prediction utilizing both a branch target buffer and a multiple target table

Hybrid branch prediction using a global selection counter and a prediction method comparison table

Address generation interlock resolution under runahead execution

Dynamic thread sharing in branch prediction structures

Perceptron branch predictor with virtualized weights

Multi-threaded processor instruction balancing through instruction uncertainty

Operand fetching control as a function of branch confidence

Global weak pattern history table filtering

Variable acknowledge rate to reduce bus contention in presence of communication errors

Method and system for power conservation in a hierarchical branch predictor

System and method for providing asynchronous dynamic millicode entry prediction

Context look ahead storage structures

Context look ahead storage structures

Dynamically adaptive associativity of a branch target buffer (BTB)

Predicting cache misses using data access behavior and instruction address

Heuristic method to control fetching of metadata from a cache hierarchy

Pointer associated branch line jumps for accelerated line jumps

Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV)

Variable branch target buffer (BTB) line size for compression

Caching of perceptron branch patterns using ternary content addressable memory based on a most influential bit location in a branch history vector

Dynamic thread sharing in branch prediction structures

Perceptron branch predictor with virtualized weights

Dynamic thread sharing in branch prediction structures

Branch prediction based on correlating events

Single thread cache miss rate estimation

Confidence threshold-based opposing branch path execution for branch prediction

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Semi-exclusive second-level branch target buffer

Confidence threshold-based opposing branch path execution for branch prediction

Cache line history tracking using an instruction address register file storing memory location identifier

Thread sparing between cores in a multi-threaded processor

BONANNO JAMES J

Asynchronous lookahead hierarchical branch prediction

State machine-based filtering of pattern history tables based on distinguishable pattern detection

Second-level branch target buffer bulk transfer filtering

Branch target buffer preload table

Global weak pattern history table filtering

Counter-based entry invalidation for metadata previous write queue

Reducing branch prediction latency using a branch target buffer with a most recently used column prediction

BUSABA FADI Y

Hardware recovery in multi-threaded processor

Reconfigurable recovery modes in high availability processors

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Variable acknowledge rate to reduce bus contention in presence of communication errors

Method and system for instruction address parity comparison

ALEXANDER GREGORY W

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

ALEXANDER KHARY J

System and method for Controlling restarting of instruction fetching using speculative address computations

JACOBI CHRISTIAN

Managing cache coherency for self-modifying code in an out-of-order execution system

EMMA PHILIP G

Branch prediction instructions having mask values involving unloading and loading branch history data

PRASKY BRIAN R

Method and apparatus to limit millicode routine end branch prediction