Inventor

PAPA RAO SATYAVOLU S

US42 patents

⚠️ This page may combine multiple inventors who share the name “PAPA RAO SATYAVOLU S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAPA RAO SATYAVOLU S

TEXAS INSTRUMENTS INC

MIM capacitors and methods for fabricating same

Systems and methods that selectively modify liner induced stress

Ferromagnetic capacitor

Measurement of wafer temperature in semiconductor processing chambers

MIM capacitors and methods for fabricating same

Method to improve inductance with a high-permeability slotted plate core in an integrated circuit

Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step

Use of supercritical fluid for low effective dielectric constant metallization

Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode

Method to improve inductance with a high-permeability slotted plate core in an integrated circuit

Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect

Dual mask capacitor for integrated circuits

Dual mask capacitor for integrated circuits

Capacitor integration at top-metal level with a protective cladding for copper surface protection

Use of supercritical fluid for low effective dielectric constant metallization

One mask high density capacitor for integrated circuits

Capacitor integration at top-metal level with a protection layer for the copper surface

Multilayer integrated circuit copper plateable barriers

Systems and methods that selectively modify liner induced stress

IBM

Semiconductor device with ballistic gate length structure

Semiconductor device with ballistic gate length structure

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom

Manufacturable sub-3 nanometer palladium gap devices for fixed electrode tunneling recognition

Nanogap in-between noble metals

Nanopore sensor device

Nanopore sensor device

Silicon surface texturing method for reducing surface reflectance

Nanogap device with capped nanowire structures

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom

Manufacturable sub-3 nanometer palladium gap devices for fixed electrode tunneling recognition

Use of metal phosphorus in metallization of photovoltaic devices and method of fabricating same

Wet clean process for removing CxHyFz etch residue

Wet clean process for removing CxHyFz etch residue

Integration of a titania layer in an anti-reflective coating

Nanogap device with capped nanowire structures

FISHER KATHRYN C

Use of metal phosphorus in metallization of photovoltaic devices and method of fabricating same

Photovoltaic device with aluminum plated back surface field and method of forming same

Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom

Single-crystalline silicon alkaline texturing with glycerol or ethylene glycol additives

Solar cells with plated back side surface field and back side electrical contact and method of fabricating same

KRISHNAN MAHADEVAIYER

Silicon surface texturing method for reducing surface reflectance

PAPA RAO SATYAVOLU S

Integration of a titania layer in an anti-reflective coating