Inventor

SHUM CHUNG-LUNG KEVIN

US56 patents

⚠️ This page may combine multiple inventors who share the name “SHUM CHUNG-LUNG KEVIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHUM CHUNG-LUNG KEVIN

IBM

Method and system for a multi-level virtual/real cache system with synonym resolution

Method and system for handling cache coherency for self-modifying code

Method and apparatus for active software disown of cache line&#39;s exlusive rights

Method, system and computer program product for sampling computer system performance data

Program store compare handling between instruction and operand caches

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

System and method for providing asynchronous dynamic millicode entry prediction

Demote instruction for relinquishing cache line ownership

Method, system, and computer program product for handling errors in a cache without processor core recovery

Method, system, and computer program product for cross-invalidation handling in a multi-level private cache

Method and system for early instruction text based operand store compare reject avoidance

System, method and computer program product for handling shared cache lines in a multi-processor environment

Method, system, and computer program product for selectively accelerating early instruction processing

Absolute address bits kept in branch history table

Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Method of implementing a translation lookaside buffer with support for a real space control

False exception for cancelled delayed requests

Generating a local clock domain using dynamic controls

Method for Quad-word Storing into 2-way interleaved L1 cache

Method, system and computer program product for generating trace data

Dynamic cache memory management with translation lookaside buffer protection

Dynamic management of memory ranges exempted from cache memory access

Reduced overhead address mode change management in a pipelined, recycling microprocessor

Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor

System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Dynamic management of a processor state with transient cache memory

Demote instruction for relinquishing cache line ownership

Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass

Dynamic management of virtual memory blocks exempted from cache memory access

System, method and computer program product for translating storage elements

System and method for providing a common instruction table

TSAI AARON

Store data forwarding with no memory model restrictions

Obtaining data in a pipelined processor

DEUTSCHLE JOERG

Method for address translation in virtual machines

ALEXANDER GREGORY W

Serializing translation lookaside buffer access around address translation parameter modification

BUSABA FADI Y

Method and system for instruction address parity comparison

EKANADHAM KATTAMURI

Enhancing timeliness of cache prefetching

BOHN RICHARD E

System, method and processor for accessing data after a translation lookaside buffer miss

SCHROTER DAVID A

Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system

KOEHLER THOMAS

Multiprocessor electronic circuit including a plurality of processors and electronic data processing system

CARLOUGH STEVEN R

Processor and method for workaround trigger activated exceptions

MAYER ULRICH

Debugging for multiple errors in a microprocessor environment

HSIEH JONATHAN T

Processor, method and computer program product for fast selective invalidation of translation lookaside buffer

FARRELL MARK S

Millicode assist instructions for millicode store access exception checking

SHUM CHUNG-LUNG KEVIN

Computer system having cache subsystem performing demote requests

Method and apparatus for active software disown of cache line's exlusive rights