Inventor

CHOU ANTHONY I

US69 patents

⚠️ This page may combine multiple inventors who share the name “CHOU ANTHONY I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU ANTHONY I

IBM

Asymmetric high-k dielectric for reducing gate induced drain leakage

Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric

Selective post-doping of gate structures by means of selective oxide growth

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Method for fabricating a nitrided silicon-oxide gate dielectric

Patterned plasma nitridation for selective epi and silicide formation

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Methods and control systems of resistance adjustment of resistors

Method and structure for SOI body contact FET with reduced parasitic capacitance

Asymmetric high-k dielectric for reducing gate induced drain leakage

Methods and control systems of resistance adjustment of resistors

Integrated circuit having local maximum operating voltage

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process

Asymmetric high-k dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Non-volatile memory device integrated with CMOS SOI FET on a single chip

Selective post-doping of gate structures by means of selective oxide growth

Dielectrics with improved leakage characteristics

Stacked FET vertical diode

Integration of nanosheets with bottom dielectric isolation and ideal diode

Heat pipe for vertically stacked field effect transistors

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process

Method and structure for a logic device and another device

Semiconductor structure with integrated passive structures

Semiconductor structure with integrated passive structures

GLOBALFOUNDRIES INC

Junction butting structure using nonuniform trench shape

High performance heat shields with reduced capacitance

Replacement gate structure for enhancing conductivity

Asymmetric semiconductor device and method of forming same

CHOU ANTHONY I

Read transistor for single poly non-volatile memory using body contacted SOI device

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Bulk substrate FET integrated on CMOS SOI

Gated diode structure and method including relaxed liner

TESSERA INC

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

CHAKRAVARTI ASHIMA B

Process for epitaxially growing epitaxial material regions

Selective deposition of germanium spacers on nitride