Inventor

AL SHEIKH RAMI MOHAMMAD

US32 patents

⚠️ This page may combine multiple inventors who share the name “AL SHEIKH RAMI MOHAMMAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AL SHEIKH RAMI MOHAMMAD

MICROSOFT TECHNOLOGY LICENSING LLC

Swapping and restoring context-specific branch predictor states on context switches in a processor

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching

Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution

Systems and methods for processing instructions having wide immediate operands

Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor

Accelerating fetch target queue (FTQ) processing in a processor

Methods and circuitry for efficient management of local branch history registers

Methods and circuitry for efficient management of local branch history registers

Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods

Performing branch predictor training using probabilistic counter updates in a processor

Reuse of branch information queue entries for multiple instances of predicted control instructions in captured loops in a processor

Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques

Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor

Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information

Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices

Selectively updating branch predictors for loops executed from loop buffers in a processor

Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata

QUALCOMM INC

Providing load address predictions using address prediction tables based on load path history in processor-based systems

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media

Intelligent data prefetching using address delta prediction

ADVANCED RISC MACH LTD

Storage of prediction-related data

Branch prediction

Combiner cache structure

Branch prediction circuitry

Branch prediction based on a predicted confidence that a corresponding function of sampled register state correlates to a later branch instruction outcome

Technique for predicting behaviour of control flow instructions

ARM LTD

Branch prediction based on sampled values