Inventor

MCADAMS HUGH P

US68 patents

⚠️ This page may combine multiple inventors who share the name “MCADAMS HUGH P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCADAMS HUGH P

TEXAS INSTRUMENTS INC

Method for initializing redundant circuitry

Computer including an integrated circuit having an on-chip high voltage source

High speed sense amplifier for MOS random access memory

Data sequencing and registering in a four bit pre-fetch SDRAM

Pin programmable dram that provides customer option programmability

Dynamic memory, a power up detection circuit, and a level detection circuit

Pin programmable dram that allows customer to program option desired

Computer including an integrated circuit having a low power selection control arrangement

Circuit, device, and method to detect voltage leakage

Low power, TTL level CMOS input buffer with hysteresis

High-speed DRAM sense amp with high noise immunity

CMOS sense amplifier with isolated sensing nodes

High-level CMOS driver circuit

Method and apparatus to reduce storage node disturbance in ferroelectric memory

Matched delay word line strap

Four bit pre-fetch sDRAM column select architecture

Substrate bias generator system

Pulse generation circuit

Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range

Low power substrate bias circuit

Test validation method for a semiconductor memory device

Cmos single input buffer for multiplexed inputs

Single sided bit line restore for power reduction

Differential plate line screen test for ferroelectric latch circuits

Methods and systems for accessing memory

Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages

Phase modulated input/output circuit

Refresh operations for semiconductor memory

F-RAM device with current mirror sense amp

Low power substrate bias circuit

Voltage level detection circuit

Apparatus and method for an address transition detector summing circuit

Apparatus and method for an address transition detector

Apparatus and method for a semiconductor memory configuration-dependent output buffer supply circuit

Matrix interconnection system with different width conductors

Low power CMOS fuse circuit

CMOS Address buffer circuit

Mid-cycle adjustment of internal clock signal timing

Dynamic memory with improved dummy cell circuitry

AGILENT TECHNOLOGIES INC

FeRAM with a single access/multiple-comparison operation

Permanent chip ID using FeRAM

Grouped plate line drive architecture and method

Dynamic reference voltage calibration integrated FeRAMS

Accuracy determination in bit line voltage measurements

On-chip compression of charge distribution data

Accelerated fatigue testing

On-chip charge distribution measurement circuit

SUMMERFELT SCOTT R

Differential plate line screen test for ferroelectric latch circuits

Differential plate line screen test for ferroelectric latch circuits

Stress buffer layer for ferroelectric random access memory