Inventor

FREEMAN GREGORY G

US47 patents

⚠️ This page may combine multiple inventors who share the name “FREEMAN GREGORY G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FREEMAN GREGORY G

IBM

Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit

Methods to improve the SiGe heterojunction bipolar device performance

Bipolar transistor with extrinsic stress layer

Process and structure for 50+ gigahertz transistor

Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border

BiCMOS integration scheme with raised extrinsic base

Method of fabricating bipolar transistors with independent impurity profile on the same chip

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack

Method of fabricating self-aligned bipolar transistor having tapered collector

Methods to improve the SiGe heterojunction bipolar device performance

Structure and method of self-aligned bipolar transistor having tapered collector

Bipolar transistor with isolation and direct contacts

Bipolar transistor with a very narrow emitter feature

Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same

Bipolar device having shallow junction raised extrinsic base and method for making the same

Stepped collector implant and method for fabrication

Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit

Creating increased mobility in a bipolar device

Bipolar transistor with collector having an epitaxial Si:C region

Bipolar structure with two base-emitter junctions in the same circuit

Method for creation of a very narrow emitter feature

Self-aligned mask formed utilizing differential oxidation rates of materials

Bipolar device having non-uniform depth base-emitter junction

Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Creating increased mobility in a bipolar device

Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same

Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border

Bipolar transistor with collector having an epitaxial Si:C region

Self-aligned mask formed utilizing differential oxidation rates of materials

Method of creating asymmetric field-effect-transistors

Methods for forming high performance gates and structures thereof

Bipolar transistor with isolation and direct contacts

Field effect transistor having an asymmetrically stressed channel region

Semiconductor device having diffusion barrier to reduce back channel leakage

Bipolar structure with two base-emitter junctions in the same circuit

High performance schottky-barrier-source asymmetric MOSFETs

GLOBALFOUNDRIES INC

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

Semiconductor device having diffusion barrier to reduce back channel leakage

Stress-generating structure for semiconductor-on-insulator devices

Reducing thermal runaway in inverter devices

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

Methods of modulating the morphology of epitaxial semiconductor material

ZHU HUILONG

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same

Stress-generating structure for semiconductor-on-insulator devices

CHOU ANTHONY I

Gated diode structure and method including relaxed liner